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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-12 16:30:47 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-15 16:10:19 +0000 |
| commit | fec6fa799ce16eabec0add9bfe6ab5222921f612 (patch) | |
| tree | 97831bc981d6209662a81ff456acbc21f893f012 /src/vendorcode/amd/agesa/f16kb | |
| parent | 5a0d29d460fa2d268e8dc1a829c75a8196302aba (diff) | |
| download | coreboot-fec6fa799ce16eabec0add9bfe6ab5222921f612.tar.xz | |
vendorcode/amd/agesa: Tidy up gcccar.inc
Change register preservations and fix comments about register
usage accordingly. Do this to avoid use of %mm0-2 registers inside
macros defined in gcccar.inc, as future implementation of
C_BOOTBLOCK_ENVIRONMENT will use them as well.
Adjust caller side accordingly.
Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/vendorcode/amd/agesa/f16kb')
| -rw-r--r-- | src/vendorcode/amd/agesa/f16kb/gcccar.inc | 23 |
1 files changed, 5 insertions, 18 deletions
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index bd670590a7..26e61da34b 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -874,7 +874,7 @@ node_core_f16_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -885,11 +885,8 @@ node_core_f16_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -949,8 +946,6 @@ node_core_f16_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1262,9 +1257,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1284,17 +1276,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1320,7 +1310,4 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm |