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| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-06-16 17:20:34 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-18 08:31:49 +0000 |
| commit | 0be23eda13a37202d21af6db346650896c3a60bd (patch) | |
| tree | 4521a2520ce3163681332c338cf1cfae6fc127b5 /src/vendorcode/amd/agesa | |
| parent | dd48b176f31fb99218ff805000d7e630f00921de (diff) | |
| download | coreboot-0be23eda13a37202d21af6db346650896c3a60bd.tar.xz | |
vendorcode/intel/fsp: Update MemInfoHob header for Jasper Lake
Jasper Lake has been using the incorrect MemInfoHob header. Updating
the header to align it with Jasper Lake MRC code.
BUG=b:158722318
TEST=Verify memory info is populated for channnel 0 and 1 on wadddledoo.
Change-Id: Icca3e3b4cda9ca257f3b725823facf52ceec37b7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src/vendorcode/amd/agesa')
0 files changed, 0 insertions, 0 deletions