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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2019-06-22 09:52:12 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-07-10 10:18:37 +0000 |
| commit | ad1456f0d7c9fcfcf6ef78969cb0e1ac6f17739a (patch) | |
| tree | b9583389468bb967af57ffdc123f51656bcd4443 /src/vendorcode/amd/cimx/sb800/SBPort.c | |
| parent | e29a6ac16a9f478fc00ce7cb83f3779954e3168d (diff) | |
| download | coreboot-ad1456f0d7c9fcfcf6ef78969cb0e1ac6f17739a.tar.xz | |
vendorcode/amd: Move 'static' to the beginning of declaration
Change-Id: Ib9934f103262c57af076bd27d97c3166d8f2318b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/amd/cimx/sb800/SBPort.c')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBPort.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/SBPort.c b/src/vendorcode/amd/cimx/sb800/SBPort.c index 048850d4bb..ba6c8f025c 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPort.c +++ b/src/vendorcode/amd/cimx/sb800/SBPort.c @@ -49,7 +49,7 @@ /** * sbPorInitPciTable - PCI device registers initial during the power on stage. */ -const static REG8MASK sbPorInitPciTable[] = +static const REG8MASK sbPorInitPciTable[] = { // SATA device {0x00, SATA_BUS_DEV_FUN, 0}, @@ -82,7 +82,7 @@ const static REG8MASK sbPorInitPciTable[] = /** * sbPmioPorInitTable - Southbridge ACPI MMIO initial during the power on stage. */ -const static AcpiRegWrite sbPmioPorInitTable[] = +static const AcpiRegWrite sbPmioPorInitTable[] = { {PMIO_BASE >> 8, SB_PMIOA_REG5D, 0x00, BIT0}, {PMIO_BASE >> 8, SB_PMIOA_REGD2, 0xCF, BIT4 + BIT5}, |