Add AMD Agesa and AMD CIMx SB800 code. Patch 1 of 8.

This code currently generates many warnings that are functionally benign.  These are being addressed, but the wheels of bureaucracy turn slowly.  This drop supports AMD cpu families 10h and 14h.  Only Family 14h is used as an example in this set of patches.  Other cpu families are supported by the infrastructure, but their specific support is not included herein.  This patch is functionally independent of the other patches in this set.

Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 523 insertions, 0 deletions

diff --git a/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h b/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
new file mode 100644
index 0000000000..eb9a701581
--- /dev/null
+++ b/src/vendorcode/amd/cimx/sb800/SBSUBFUN.h
@@ -0,0 +1,523 @@
+/**
+ * @file
+ *
+ * Southbridge CIMx Function Support Define (All)
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project:      CIMx-SB
+ * @e sub-project:
+ * @e \$Revision:$   @e \$Date:$
+ *
+ */
+/*
+ *****************************************************************************
+ *
+ * Copyright (c) 2011, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Advanced Micro Devices, Inc. nor the names of 
+ *       its contributors may be used to endorse or promote products derived 
+ *       from this software without specific prior written permission.
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ * ***************************************************************************
+ *
+ */
+
+// Southbridge SBMAIN Routines
+
+/**
+ * Southbridge Main Function Public Function
+ *
+ */
+
+/**
+ * sbBeforePciInit - Config Southbridge before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbBeforePciInit (IN AMDSBCFG* pConfig);
+
+
+/**
+ * sbAfterPciInit - Config Southbridge after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbAfterPciInit (IN AMDSBCFG* pConfig);
+
+/**
+ *  sbMidPostInit - Config Southbridge during middle of POST
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbMidPostInit (IN AMDSBCFG* pConfig);
+
+/**
+ *  sbLatePost - Prepare Southbridge to boot to OS.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbLatePost (IN AMDSBCFG* pConfig);
+
+/**
+ * sbBeforePciRestoreInit - Config Southbridge before ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbBeforePciRestoreInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbAfterPciRestoreInit - Config Southbridge after ACPI S3 resume PCI config device restore
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbAfterPciRestoreInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbSmmAcpiOn - Config Southbridge during ACPI_ON
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbSmmAcpiOn (IN AMDSBCFG* pConfig);
+
+/**
+ * CallBackToOEM - Call Back routine.
+ *
+ *
+ *
+ * @param[in] Func    Callback ID.
+ * @param[in] Data    Callback specific data.
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ */
+unsigned int CallBackToOEM (IN unsigned int Func, IN unsigned int Data, IN AMDSBCFG* pConfig);
+
+
+// Southbridge SBPOR Routines
+
+/**
+ * Southbridge power-on initial Public Function
+ *
+ */
+
+/**
+ * sbPowerOnInit - Config Southbridge during power on stage.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPowerOnInit (IN AMDSBCFG* pConfig);
+
+
+// Southbridge Common Routines
+
+/**
+ * Southbridge Common Public Function
+ *
+ */
+
+/**
+ * commonInitEarlyBoot - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ *    This settings should be done during S3 resume also
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitEarlyBoot (IN AMDSBCFG* pConfig);
+
+/**
+ * commonInitEarlyPost - Config Southbridge SMBUS/ACPI/IDE/LPC/PCIB.
+ *
+ *    This settings might not program during S3 resume
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitEarlyPost (IN AMDSBCFG* pConfig);
+
+/**
+ * commonInitLateBoot - Prepare Southbridge register setting to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void commonInitLateBoot (IN AMDSBCFG* pConfig);
+
+/**
+ * abSpecialSetBeforePciEnum - Special setting ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void abSpecialSetBeforePciEnum (IN AMDSBCFG* pConfig);
+
+void usbSetPllDuringS3 (IN AMDSBCFG* pConfig);
+void usbDesertPll (IN AMDSBCFG* pConfig);
+
+/**
+ * hpetInit - Program Southbridge HPET function
+ *
+ *  ** Eric
+ *
+ * @param[in] pConfig         Southbridge configuration structure pointer.
+ * @param[in] pStaticOptions  Platform build configuration table.
+ *
+ */
+void hpetInit (IN AMDSBCFG* pConfig, IN BUILDPARAM *pStaticOptions);
+
+/**
+ * c3PopupSetting - Program Southbridge C state function
+ *
+ *  ** Eric
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+void c3PopupSetting (IN AMDSBCFG* pConfig);
+
+/**
+ * FusionRelatedSetting - Program Fusion C related function
+ *
+ *
+ *
+ * @param[in] pConfig   Southbridge configuration structure pointer.
+ *
+ */
+void FusionRelatedSetting (IN AMDSBCFG* pConfig);
+
+/**
+ * Southbridge Common Private Function
+ *
+ */
+
+/**
+ * abLinkInitBeforePciEnum - Set ABCFG registers before PCI emulation.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void abLinkInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+// Southbridge SATA Routines
+
+/**
+ * Southbridge SATA Controller Public Function
+ *
+ */
+
+/**
+ * sataInitMidPost - Config SATA controller in Middle POST.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sataInitMidPost (IN AMDSBCFG* pConfig);
+
+/**
+ * sataInitAfterPciEnum - Config SATA controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void  sataInitAfterPciEnum (IN AMDSBCFG*   pConfig);
+
+/**
+ * sataInitBeforePciEnum - Config SATA controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void  sataInitBeforePciEnum (IN AMDSBCFG*  pConfig);
+
+/**
+ * sataInitLatePost - Prepare SATA controller to boot to OS.
+ *
+ *              - Set class ID to AHCI (if set to AHCI * Mode)
+ *              - Enable AHCI interrupt
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void  sataInitLatePost (IN AMDSBCFG* pConfig);
+
+// Southbridge GEC Routines
+
+/**
+ * Southbridge GEC Controller Public Function
+ *
+ */
+
+/**
+ * gecInitBeforePciEnum - Config GEC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitBeforePciEnum (IN AMDSBCFG*   pConfig);
+
+/**
+ * gecInitAfterPciEnum - Config GEC controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitAfterPciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * gecInitLatePost - Prepare GEC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void gecInitLatePost (IN AMDSBCFG* pConfig);
+
+// Southbridge USB Routines
+
+/**
+ * Southbridge USB Controller Public Function
+ *
+ */
+
+/**
+ * Config USB controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usbInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Config USB controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usbInitAfterPciInit (IN AMDSBCFG* pConfig);
+
+/**
+ * Config USB1 EHCI controller after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void usb1EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb2EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb3EhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb1OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb2OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb3OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+void usb4OhciInitAfterPciInit (IN AMDSBCFG* pConfig);
+
+// Southbridge SMI Service Routines (SMM.C)
+
+/**
+ * Southbridge SMI Service Routines Public Function
+ *
+ */
+
+/**
+ * Southbridge SMI service module
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbSmmService (IN AMDSBCFG* pConfig);
+
+/**
+ * softwareSMIservice - Software SMI service
+ *
+ *  ** Eric
+ *
+ * @param[in] void Southbridge software SMI service ID.
+ *
+ */
+void softwareSMIservice (IN void);
+
+// Southbridge GPP Controller Routines
+
+/**
+ * Southbridge GPP Controller Routines Public Function
+ *
+ */
+
+/**
+ * GPP early programming and link training. On exit all populated EPs should be fully operational.
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPcieGppEarlyInit (IN AMDSBCFG* pConfig);
+
+/**
+ * sbPcieGppLateInit - Late PCIE initialization for SB800 GPP component
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void sbPcieGppLateInit (IN AMDSBCFG* pConfig);
+
+// Southbridge HD Controller Routines (AZALIA.C)
+
+/**
+ * Southbridge HD Controller Routines (AZALIA.C) Public Function
+ *
+ */
+
+/**
+ * Config HD Audio Before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void azaliaInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Config HD Audio after PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+void azaliaInitAfterPciEnum (IN AMDSBCFG* pConfig);
+
+
+// Southbridge EC Routines
+
+#ifndef NO_EC_SUPPORT
+/**
+ * Southbridge EC Controller Public Function
+ *
+ */
+
+/**
+ * Config EC controller during power-on
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  ecPowerOnInit (IN AMDSBCFG* pConfig);
+
+/**
+ * Config EC controller before PCI emulation
+ *
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  ecInitBeforePciEnum (IN AMDSBCFG* pConfig);
+
+/**
+ * Prepare EC controller to boot to OS.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  ecInitLatePost (IN AMDSBCFG* pConfig);
+
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ * @retval        TRUE   Pass
+ * @retval        FALSE     Failed
+ */
+  unsigned char  validateImcFirmware (IN AMDSBCFG* pConfig);
+
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  softwareToggleImcStrapping (IN AMDSBCFG* pConfig);
+#endif
+
+#ifndef NO_HWM_SUPPORT
+/**
+ * validateImcFirmware - Validate IMC Firmware.
+ *
+ *
+ * @param[in] pConfig Southbridge configuration structure pointer.
+ *
+ */
+  void  hwmInit (IN AMDSBCFG* pConfig);
+#endif
+