diff options
| author | Kerry She <kerry.she@amd.com> | 2011-06-01 01:56:49 +0000 |
|---|---|---|
| committer | Kerry She <Kerry.She@amd.com> | 2011-06-01 01:56:49 +0000 |
| commit | 991f8808933a8b528108dcd48a029ebf40b05c6b (patch) | |
| tree | d08e8791ab01d76df137a984f0fed1a91cab5632 /src/vendorcode/amd/cimx/sb800 | |
| parent | b2ecd8151481af7c5a74ed61967ad9698486253e (diff) | |
| download | coreboot-991f8808933a8b528108dcd48a029ebf40b05c6b.tar.xz | |
This patch fix a AMD sb800 wrapper compile warning:
src/southbridge/amd/cimx_wrapper/sb800/late
call clear_ioapic but not include the prototype declare header file.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/vendorcode/amd/cimx/sb800')
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/EC.c | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SATA.c | 4 | ||||
| -rw-r--r-- | src/vendorcode/amd/cimx/sb800/SBTYPE.h | 8 |
3 files changed, 8 insertions, 8 deletions
diff --git a/src/vendorcode/amd/cimx/sb800/EC.c b/src/vendorcode/amd/cimx/sb800/EC.c index 220424f905..633d251624 100644 --- a/src/vendorcode/amd/cimx/sb800/EC.c +++ b/src/vendorcode/amd/cimx/sb800/EC.c @@ -71,7 +71,7 @@ ecPowerOnInit ( RWEC8 (0x61, 0x00, (MailBoxPort & 0xFF)); //set LSB of Mailbox port RWEC8 (0x30, 0x00, 0x01); //;Enable Mailbox Registers Interface, bit0=1 - if ( pConfig->BuildParameters.EcKbd == ENABLED) { + if ( pConfig->BuildParameters.EcKbd == CIMX_OPTION_ENABLED) { //Enable KBRST#, IRQ1 & IRQ12, GateA20 Function signal from IMC RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGD6, AccWidthUint8, ~BIT8, BIT0 + BIT1 + BIT2 + BIT3); @@ -83,7 +83,7 @@ ecPowerOnInit ( RWEC8 (0x30, 0x00, 0x01); } - if ( pConfig->BuildParameters.EcChannel0 == ENABLED) { + if ( pConfig->BuildParameters.EcChannel0 == CIMX_OPTION_ENABLED) { //Logical device 0x03 RWEC8 (0x07, 0x00, 0x03); RWEC8 (0x60, 0x00, 0x00); diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index 0f85f3a190..5777d3adfe 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -470,7 +470,7 @@ sataInitAfterPciEnum ( if (((pConfig->SataClass) != NATIVE_IDE_MODE) && ((pConfig->SataClass) != LEGACY_IDE_MODE)) { // RIAD or AHCI - if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { + if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { RWMEM ((ddBar5 + SB_SATA_BAR5_REG00), AccWidthUint8 | S3_SAVE, ~(BIT2 + BIT1 + BIT0), BIT2 + BIT0); RWMEM ((ddBar5 + SB_SATA_BAR5_REG0C), AccWidthUint8 | S3_SAVE, 0xC0, 0x3F); // RPR 8.10 Disabling CCC (Command Completion Coalescing) support. @@ -631,7 +631,7 @@ sataInitLatePost ( //Enable write access to pci header, pm capabilities RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40), AccWidthUint8 | S3_SAVE, 0xff, BIT0); -// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == DISABLED) { +// if ((pConfig->SATAMODE.SataMode.SataIdeCombinedMode) == CIMX_OPTION_DISABLED) { RWPCI (((SATA_BUS_DEV_FUN << 16) + SB_SATA_REG40 + 1), AccWidthUint8 | S3_SAVE, ~BIT7, BIT7); // } sataBar5setting (pConfig, &ddBar5); diff --git a/src/vendorcode/amd/cimx/sb800/SBTYPE.h b/src/vendorcode/amd/cimx/sb800/SBTYPE.h index 4ba7140f7f..ea3e6f6c42 100644 --- a/src/vendorcode/amd/cimx/sb800/SBTYPE.h +++ b/src/vendorcode/amd/cimx/sb800/SBTYPE.h @@ -1093,13 +1093,13 @@ typedef unsigned int CIM_STATUS; #pragma pack (pop) /** - * DISABLED - Define disable in module + * CIMX_OPTION_DISABLED - Define disable in module */ -#define DISABLED 0 +#define CIMX_OPTION_DISABLED 0 /** - * ENABLED - Define enable in module + * CIMX_OPTION_ENABLED - Define enable in module */ -#define ENABLED 1 +#define CIMX_OPTION_ENABLED 1 // mov al, code // out 80h, al |