amd/cimx: fix sb(8|9)00 NULL type redefine

It is inappropriate for chipset code to be redefining
types -- especially NULL to a non-pointer type. There's
only one non-straight forward change. A condition
being checked was '!ptr_type == NULL' (0 as int). That
check is actually 'ptr_type != NULL'.

Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5088
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

5 files changed, 8 insertions, 8 deletions

diff --git a/src/vendorcode/amd/cimx/sb900/Azalia.c b/src/vendorcode/amd/cimx/sb900/Azalia.c
index 3fe4647aab..7a1277cbe5 100644
--- a/src/vendorcode/amd/cimx/sb900/Azalia.c
+++ b/src/vendorcode/amd/cimx/sb900/Azalia.c
@@ -282,7 +282,7 @@ azaliaInitAfterPciEnum (
 
   if ( pConfig->AzaliaController != 1 ) {
     RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG04, AccWidthUint8 | S3_SAVE, ~BIT1, BIT1);
-    if ( pConfig->BuildParameters.AzaliaSsid != NULL ) {
+    if ( pConfig->BuildParameters.AzaliaSsid != 0 ) {
       RWPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.AzaliaSsid);
     }
     ReadPCI ((AZALIA_BUS_DEV_FUN << 16) + SB_AZ_REG10, AccWidthUint32, &ddBAR0);
diff --git a/src/vendorcode/amd/cimx/sb900/Gec.c b/src/vendorcode/amd/cimx/sb900/Gec.c
index cfd830d0f3..4afd6e981d 100644
--- a/src/vendorcode/amd/cimx/sb900/Gec.c
+++ b/src/vendorcode/amd/cimx/sb900/Gec.c
@@ -109,7 +109,7 @@ gecInitAfterPciEnum (
   VOID* GecRomAddress;
   VOID* GecShadowRomAddress;
   UINT32 ddTemp;
-  if ( !pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr == NULL ) {
+  if ( pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr != NULL ) {
     GecRomAddress = pConfig->DYNAMICGECROM.DynamicGecRomAddress_Ptr;
     GecShadowRomAddress = (VOID*) (UINTN) pConfig->BuildParameters.GecShadowRomBase;
     AmdSbCopyMem (GecShadowRomAddress, GecRomAddress, 0x100);
diff --git a/src/vendorcode/amd/cimx/sb900/Sata.c b/src/vendorcode/amd/cimx/sb900/Sata.c
index fca8005ee0..5c3a621bb4 100644
--- a/src/vendorcode/amd/cimx/sb900/Sata.c
+++ b/src/vendorcode/amd/cimx/sb900/Sata.c
@@ -458,7 +458,7 @@ sataInitBeforePciEnum (
     //Set PATA controller to native mode
     RWPCI (((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG09), AccWidthUint8 | S3_SAVE, 0x00, 0x08F);
   }
-  if (pConfig->BuildParameters.IdeSsid != NULL ) {
+  if (pConfig->BuildParameters.IdeSsid != 0 ) {
     RWPCI ((IDE_BUS_DEV_FUN << 16) + SB_IDE_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.IdeSsid);
   }
   // SATA Controller Class ID & SSID
diff --git a/src/vendorcode/amd/cimx/sb900/SbCmn.c b/src/vendorcode/amd/cimx/sb900/SbCmn.c
index 29f6fd1d80..bd50ddeb22 100644
--- a/src/vendorcode/amd/cimx/sb900/SbCmn.c
+++ b/src/vendorcode/amd/cimx/sb900/SbCmn.c
@@ -398,7 +398,7 @@ commonInitEarlyBoot (
   RWMEM (ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGC8 + 1, AccWidthUint8, ~BIT6, 0);
   //Early post initialization of pci config space
   programPciByteTable ((REG8MASK*) FIXUP_PTR (&sbEarlyPostByteInitTable[0]), sizeof (sbEarlyPostByteInitTable) / sizeof (REG8MASK) );
-  if ( pConfig->BuildParameters.SmbusSsid != NULL ) {
+  if ( pConfig->BuildParameters.SmbusSsid != 0 ) {
     RWPCI ((SMBUS_BUS_DEV_FUN << 16) + SB_CFG_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.SmbusSsid);
   }
   //Make BAR registers of smbus invisible.
@@ -408,7 +408,7 @@ commonInitEarlyBoot (
   // LPC CFG programming
   //
   // SSID for LPC Controller
-  if (pConfig->BuildParameters.LpcSsid != NULL ) {
+  if (pConfig->BuildParameters.LpcSsid != 0 ) {
     RWPCI ((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.LpcSsid);
   }
   // LPC MSI
diff --git a/src/vendorcode/amd/cimx/sb900/Usb.c b/src/vendorcode/amd/cimx/sb900/Usb.c
index 2ae03b3f6d..2d635ec9ee 100644
--- a/src/vendorcode/amd/cimx/sb900/Usb.c
+++ b/src/vendorcode/amd/cimx/sb900/Usb.c
@@ -357,7 +357,7 @@ EhciInitAfterPciInit (
   if ( (ddBarAddress != - 1) && (ddBarAddress != 0) ) {
     //Enable Memory access
     RWPCI ((UINT32) Value + SB_EHCI_REG04, AccWidthUint8, 0, BIT1);
-    if (pConfig->BuildParameters.EhciSsid != NULL ) {
+    if (pConfig->BuildParameters.EhciSsid != 0 ) {
       RWPCI ((UINT32) Value + SB_EHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.EhciSsid);
     }
     //USB Common PHY CAL & Control Register setting
@@ -571,7 +571,7 @@ usb4OhciInitAfterPciInit (
   UINT32  ddDeviceId;
   ddDeviceId = (USB4_OHCI_BUS_DEV_FUN << 16);
   OhciInitAfterPciInit (ddDeviceId, pConfig);
-  if (pConfig->BuildParameters.Ohci4Ssid != NULL ) {
+  if (pConfig->BuildParameters.Ohci4Ssid != 0 ) {
     RWPCI ((USB4_OHCI_BUS_DEV_FUN << 16) + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.Ohci4Ssid);
   }
 }
@@ -595,7 +595,7 @@ OhciInitAfterPciInit (
   // RPR USB SMI Handshake
   RWPCI ((UINT32) Value + SB_OHCI_REG50 + 1, AccWidthUint8 | S3_SAVE, ~BIT4, 0x00);
   if (Value != (USB4_OHCI_BUS_DEV_FUN << 16)) {
-    if ( pConfig->BuildParameters.OhciSsid != NULL ) {
+    if ( pConfig->BuildParameters.OhciSsid != 0 ) {
       RWPCI ((UINT32) Value + SB_OHCI_REG2C, AccWidthUint32 | S3_SAVE, 0x00, pConfig->BuildParameters.OhciSsid);
     }
   }