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| author | Felix Held <felix-coreboot@felixheld.de> | 2021-04-21 21:21:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-21 11:22:59 +0000 |
| commit | 7608ea0c9f6c8763bd80628adf2d977e60823275 (patch) | |
| tree | d9dfab540638a69c1b2498075f88e8479af5c1fa /src/vendorcode/amd/fsp/picasso/FspGuids.h | |
| parent | b192af12e3e483699f2e75790b2eb6e79b5b4f71 (diff) | |
| download | coreboot-7608ea0c9f6c8763bd80628adf2d977e60823275.tar.xz | |
soc/amd/cezanne,common,picasso: use BERT region reserved by FSP driver
commit ce0e2a014009390c4527e064efb59260ef4d3a3b (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.
BUG=b:169934025
TEST=BERT table that gets generated in a follow-up patch for Picasso
points to expected BERT region and Linux is able to access, decode and
display it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/fsp/picasso/FspGuids.h')
| -rw-r--r-- | src/vendorcode/amd/fsp/picasso/FspGuids.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h index 70bbe74d96..64bf97c8f3 100644 --- a/src/vendorcode/amd/fsp/picasso/FspGuids.h +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -9,10 +9,6 @@ GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) -#define AMD_FSP_BERT_HOB_GUID \ - GUID_INIT(0xa21f7ab5, 0x6a89, 0x4df2, \ - 0xb9, 0x19, 0x51, 0xad, 0x95, 0x50, 0x5b, 0xd8) - #define AMD_FSP_ACPI_SSDT_HOB_GUID \ GUID_INIT(0x54445353, 0x4002, 0x403b, \ 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) |