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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-12 16:30:47 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2017-07-15 16:08:59 +0000 |
commit | bfe6bcab746aff5c765b901c8f8e5a1e23bad186 (patch) | |
tree | fddd8a6e36ca4494dfa62e743a18c156de7df1f0 /src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc | |
parent | 7f5d0f3c922ee22f7347d1b5d275508b8b9e8ce9 (diff) | |
download | coreboot-bfe6bcab746aff5c765b901c8f8e5a1e23bad186.tar.xz |
vendorcode/amd/pi: Tidy up gcccar.inc
Remove register preservations that are not required and
fix comments about register usage accordingly.
Change-Id: Ibc9ed982ac55e947c100739250db122033348a82
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20576
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc')
-rw-r--r-- | src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc | 23 |
1 files changed, 5 insertions, 18 deletions
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc index 11376d50c7..4092dbf971 100644 --- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc +++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc @@ -1164,7 +1164,7 @@ node_core_f15_exit: * AMD_ENABLE_STACK: Setup a stack * * In: -* EBX = Return address (preserved) +* No inputs * * Out: * SS:ESP - Our new private stack location @@ -1175,11 +1175,8 @@ node_core_f15_exit: * * Requirements: * * This routine presently is limited to a max of 64 processor cores -* Preserved: -* ebx ebp * Destroyed: -* eax, ecx, edx, edi, esi, ds, es, ss, esp -* mmx0, mmx1 +* EBX, EDX, EDI, ESI, EBP, DS, ES * * Description: * Fixed MTRR address allocation to cores: @@ -1239,8 +1236,6 @@ node_core_f15_exit: # Note that SS:ESP will be default stack. Note that this stack # routine will not be used after memory has been initialized. Because # of its limited lifetime, it will not conflict with typical PCI devices. - movd %ebx, %mm0 # Put return address in a safe place - movd %ebp, %mm1 # Save some other user registers # get node id and core id of current executing core GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node) @@ -1554,9 +1549,6 @@ ClearTheStack: # Stack base is in SS, stack pointer is or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up) #.endif 0: - - movd %mm0, %ebx # Restore return address - movd %mm1, %ebp .endm /***************************************************************************** @@ -1576,17 +1568,15 @@ ClearTheStack: # Stack base is in SS, stack pointer is * none * * Out: -* EAX = AGESA_SUCCESS +* none * * Preserved: -* ebx +* ESP * Destroyed: -* eax, ecx, edx, esp +* EAX, EBX, ECX, EDX, EDI, ESI *****************************************************************************/ .macro AMD_DISABLE_STACK - mov %ebx, %esp # Save return address - # get node/core/flags of current executing core GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node) @@ -1612,8 +1602,5 @@ ClearTheStack: # Stack base is in SS, stack pointer is AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations - mov %esp, %ebx - xor %eax, %eax - .endm |