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| author | Richard Spiegel <richard.spiegel@amd.corp-partner.google.com> | 2018-05-07 07:53:42 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-09 10:12:33 +0000 |
| commit | 4bb706555ec84e00948c65993d03f1ee1c2a83eb (patch) | |
| tree | 21a4746f17ee36b9c90f172789dcac536cc6075f /src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c | |
| parent | 9c1dc7cbe17cc77636c7c7121c3ccb1dbb55c7b7 (diff) | |
| download | coreboot-4bb706555ec84e00948c65993d03f1ee1c2a83eb.tar.xz | |
vendorcode/amd/pi/00670F00: Control which procedure builds
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.
BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.
Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c')
| -rw-r--r-- | src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c index 1739c70167..2989265b42 100644 --- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c +++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c @@ -223,6 +223,7 @@ GetPspDirBase ( return (FALSE); } +#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /** * Get specific PSP Entry information, this routine will auto detect the processor for loading * correct PSP Directory @@ -329,6 +330,7 @@ UpdataPspDirCheckSum ( PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \ (sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2); } +#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ /** Check if PSP device is present @@ -351,6 +353,7 @@ CheckPspDevicePresent ( return (FALSE); } +#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /** Check PSP Platform Seucre Enable State HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode) @@ -418,6 +421,7 @@ GetPspMboxStatus ( return (TRUE); } +#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ BOOLEAN PspBarInitEarly () @@ -454,6 +458,7 @@ PspBarInitEarly () return (TRUE); } +#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /** Return the PspMMIO MMIO location @@ -478,6 +483,7 @@ GetPspBar1Addr ( return (TRUE); } +#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ /** Return the PspMMIO MMIO location @@ -513,6 +519,7 @@ GetPspBar3Addr ( return (TRUE); } +#if IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) /** * Acquire the Mutex for access PSP,X86 co-accessed register * Call this routine before access SMIx98 & SMIxA8 @@ -679,4 +686,5 @@ IsS3Resume ( return ((SleepType == 3) ? TRUE : FALSE); } +#endif /* IS_ENABLED(CONFIG_VENDORCODE_FULL_SUPPORT) */ |