vendorcode/amd: Copy 00670F00 files from PI package

Make exact copies of the AGESA files from the Stoney PI package
replacing existing versions.  Change the license text and fix
up misc. whitespace.

This will facilitate the review of binaryPI changes in the
vendorcode directory.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1097249585ab76fab59dcfbf8e7a419f34fcfcb6)

Change-Id: I9951df58aeab2d533efc0a837ce35f343ff28d7c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17194
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

3 files changed, 311 insertions, 41 deletions

diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
index 20a359ad0e..5c2410d7d4 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.c
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  PSP
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -48,10 +48,11 @@
  */
 #include "AGESA.h"
 #include "Filecode.h"
+#include "Fch.h"
 #include "PspBaseLib.h"
 
 #define FILECODE PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE
-#define PSP_BAR1_TMP_BASE 0xFEA00000ul
+#define PSP_BAR_TMP_BASE 0xFEA00000ul
 
 #define GET_PCI_BUS(Reg) (((UINT32) Reg >> 16) & 0xFF)
 #define GET_PCI_DEV(Reg) (((UINT32) Reg >> 11) & 0x1F)
@@ -74,6 +75,13 @@
 #define PSP_SECURE_PART                 (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE)      ///< Secure Part
 #define PSP_FRA_MODE                    (SMU_CC_PSP_FUSES_FRA_ENABLE + SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE)  ///< FRA Part
 
+#define PSP_MUTEX_REG0_OFFSET     (24 * 4)       ///< PSP Mutex0 register offset
+#define PSP_MUTEX_REG1_OFFSET     (25 * 4)       ///< PSP Mutex1 register offset
+
+#ifndef OFFSET_OF
+#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field))
+#endif
+
 /*----------------------------------------------------------------------------------------
  *                   D E F I N I T I O N S    A N D    M A C R O S
  *----------------------------------------------------------------------------------------
@@ -139,6 +147,37 @@ PspLibPciWritePspConfig (
   PspLibPciWriteConfig  ((UINT32) (PSP_PCI_BDA  + Offset), Value);
 }
 
+/// Structure for Program ID
+typedef enum {
+  CZ_PROGRAM = 0x00,            ///< Program ID for CZ
+  BR_PROGRAM = 0x01,            ///< Program ID for BR
+  ST_PROGRAM = 0x02,            ///< Program ID for ST
+  UNSUPPORTED_PROGRAM = 0xFF,   ///< Program ID for unsupported
+} PROGRAM_ID;
+
+PROGRAM_ID
+PspGetProgarmId (
+  VOID
+  )
+{
+  CPUID_DATA          Cpuid;
+
+  LibAmdCpuidRead (0x00000001, &Cpuid, NULL);
+  //Stoney CPUID 0x00670F00 or 0x00670F01
+  if ((Cpuid.EAX_Reg >> 16) == 0x67) {
+    return ST_PROGRAM;
+  } else if ((Cpuid.EAX_Reg >> 16) == 0x66) {
+    if ((Cpuid.EAX_Reg & 0xF0) == 0x50) {
+      //Bristol CPUID 0x00660F51
+      return BR_PROGRAM;
+    } else if ((Cpuid.EAX_Reg & 0xF0) == 0x00) {
+      //Carrizo CPUID 0x00660F00 or 0x00660F01
+      return CZ_PROGRAM;
+    }
+  }
+  return UNSUPPORTED_PROGRAM;
+}
+
 BOOLEAN
 GetPspDirBase (
   IN OUT   UINT32     *Address
@@ -146,6 +185,7 @@ GetPspDirBase (
 {
   UINTN                     i;
   FIRMWARE_ENTRY_TABLE      *FirmwareTableBase;
+  PROGRAM_ID                ProgramId;
   CONST UINT32 RomSigAddrTable[] =
   {
     0xFFFA0000, //  --> 512KB base
@@ -156,32 +196,66 @@ GetPspDirBase (
     0xFF020000  //  --> 16MB base
   };
 
+  ProgramId = PspGetProgarmId ();
+
   for (i = 0; i < sizeof (RomSigAddrTable) / sizeof (UINT32); i++) {
     FirmwareTableBase  = (FIRMWARE_ENTRY_TABLE *) (UINTN) RomSigAddrTable[i];
     // Search flash for unique signature 0x55AA55AA
     if (FirmwareTableBase->Signature  == FIRMWARE_TABLE_SIGNATURE) {
-      *Address = FirmwareTableBase->PspDirBase;
+      switch (ProgramId) {
+      case BR_PROGRAM:
+      case CZ_PROGRAM:
+        *Address = FirmwareTableBase->PspDirBase;
+        break;
+      case ST_PROGRAM:
+        *Address = FirmwareTableBase->NewPspDirBase;
+        break;
+      default:
+        *Address = FirmwareTableBase->PspDirBase;
+        break;
+      }
       return TRUE;
     }
   }
-
   return (FALSE);
 }
 
+/**
+ * Get specific PSP Entry information, this routine will auto detect the processor for loading
+ * correct PSP Directory
+ *
+ *
+ *
+ * @param[in] EntryType               PSP DIR Entry Type
+ * @param[in,out] EntryAddress        Address of the specific PSP Entry
+ * @param[in,out] EntrySize           Size of the specific PSP Entry
+ */
+
 BOOLEAN
 PSPEntryInfo (
   IN       PSP_DIRECTORY_ENTRY_TYPE    EntryType,
   IN OUT   UINT64                      *EntryAddress,
-  IN       UINT32                      *EntrySize
+  IN OUT   UINT32                      *EntrySize
   )
 {
   PSP_DIRECTORY         *PspDir;
   UINTN                 i;
+  PROGRAM_ID                ProgramId;
 
+  PspDir = NULL;
   if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
     return FALSE;
   }
 
+  ProgramId = PspGetProgarmId ();
+  //Append BR Program ID
+  if ((ProgramId == BR_PROGRAM) &&
+      ((EntryType == SMU_OFFCHIP_FW) ||
+       (EntryType == SMU_OFF_CHIP_FW_2) ||
+       (EntryType == AMD_SCS_BINARY))) {
+    EntryType |= (PSP_ENTRY_BR_PROGRAM_ID << 8);
+  }
+
   for (i = 0; i < PspDir->Header.TotalEntries; i++) {
     if (PspDir->PspEntry[i].Type == EntryType) {
       *EntryAddress = PspDir->PspEntry[i].Location;
@@ -193,6 +267,66 @@ PSPEntryInfo (
   return (FALSE);
 }
 
+BOOLEAN
+PspSoftWareFuseInfo (
+  IN OUT   UINTN                       *FuseSpiAddress,
+  IN OUT   UINT64                      *FuseValue
+  )
+{
+  PSP_DIRECTORY         *PspDir;
+  UINTN                 i;
+
+  PspDir = NULL;
+  if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
+    return FALSE;
+  }
+
+  for (i = 0; i < PspDir->Header.TotalEntries; i++) {
+    if (PspDir->PspEntry[i].Type == AMD_SOFT_FUSE_CHAIN_01) {
+      *FuseSpiAddress = (UINT32) (UINTN) &PspDir->PspEntry[i].Location;
+      *FuseValue = PspDir->PspEntry[i].Location;
+      return (TRUE);
+    }
+  }
+  return (FALSE);
+}
+
+UINT32 Fletcher32 (
+  IN OUT   UINT16  *data,
+  IN       UINTN   words
+  )
+{
+  UINT32 sum1;
+  UINT32 sum2;
+  UINTN tlen;
+
+  sum1 = 0xffff;
+  sum2 = 0xffff;
+
+  while (words) {
+    tlen = words >= 359 ? 359 : words;
+    words -= tlen;
+    do {
+      sum2 += sum1 += *data++;
+    } while (--tlen);
+    sum1 = (sum1 & 0xffff) + (sum1 >> 16);
+    sum2 = (sum2 & 0xffff) + (sum2 >> 16);
+  }
+  // Second reduction step to reduce sums to 16 bits
+  sum1 = (sum1 & 0xffff) + (sum1 >> 16);
+  sum2 = (sum2 & 0xffff) + (sum2 >> 16);
+  return sum2 << 16 | sum1;
+}
+
+VOID
+UpdataPspDirCheckSum (
+  IN OUT   PSP_DIRECTORY         *PspDir
+  )
+{
+    PspDir->Header.Checksum = Fletcher32 ((UINT16 *) &PspDir->Header.TotalEntries, \
+      (sizeof (PSP_DIRECTORY_HEADER) - OFFSET_OF (PSP_DIRECTORY_HEADER, TotalEntries) + PspDir->Header.TotalEntries * sizeof (PSP_DIRECTORY_ENTRY)) / 2);
+}
+
 /**
   Check if PSP device is present
 
@@ -273,7 +407,7 @@ GetPspMboxStatus (
 {
   UINT32 PspMmio;
 
-  if (GetPspBar1Addr (&PspMmio) == FALSE) {
+  if (GetPspBar3Addr (&PspMmio) == FALSE) {
     return (FALSE);
   }
 
@@ -283,7 +417,7 @@ GetPspMboxStatus (
 }
 
 BOOLEAN
-PspBarInitEarly (void)
+PspBarInitEarly ()
 {
   UINT32 PspMmioSize;
   UINT32 Value32;
@@ -293,18 +427,18 @@ PspBarInitEarly (void)
   }
 
   //Check if PSP BAR has been assigned, if not do the PSP BAR initialation
-  if (PspLibPciReadPspConfig (PSP_PCI_BAR1_REG) == 0) {
+  if (PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) == 0) {
     /// Get PSP BAR1 Size
-    PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, 0xFFFFFFFF);
-    PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG);
+    PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, 0xFFFFFFFF);
+    PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG);
     PspMmioSize = ~PspMmioSize + 1;
-    /// Assign BAR1 Temporary Address
-    PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, PSP_BAR1_TMP_BASE);
+    /// Assign BAR3 Temporary Address
+    PspLibPciWritePspConfig (PSP_PCI_BAR3_REG, PSP_BAR_TMP_BASE);
     PspLibPciWritePspConfig ( PSP_PCI_CMD_REG, 0x06);
 
     /// Enable GNB redirection to this space @todo use equate & also find proper fix
-    PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR1_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF);
-    PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR1_TMP_BASE >> 8) | 3);
+    PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF);
+    PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR_TMP_BASE >> 8) | 3);
     /// Enable MsixBarEn, Bar1En, Bar3En
     PspLibPciWritePspConfig ( PSP_PCI_EXTRAPCIHDR_REG, 0x34);
     /// Capability chain update
@@ -354,11 +488,21 @@ GetPspBar3Addr (
   IN OUT   UINT32 *PspMmio
   )
 {
+  UINT32 PciReg48;
+  UINT64 MsrPspAddr;
+
   if (CheckPspDevicePresent () == FALSE) {
     return (FALSE);
   }
 
-  *PspMmio = PspLibPciReadPspConfig  (PSP_PCI_BAR3_REG);
+  PciReg48 = PspLibPciReadPspConfig (PSP_PCI_EXTRAPCIHDR_REG);
+  if (PciReg48 & BIT12) {
+  // D8F0x48[12] Bar3Hide
+    LibAmdMsrRead (PSP_MSR_PRIVATE_BLOCK_BAR, &MsrPspAddr, NULL);
+    *PspMmio = (UINT32)MsrPspAddr;
+  } else {
+    *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG) & 0xFFF00000;
+  }
 
   if ((*PspMmio) == 0xffffffff) {
     return (FALSE);
@@ -366,6 +510,51 @@ GetPspBar3Addr (
 
   return (TRUE);
 }
+/**
+ * Acquire the Mutex for access PSP,X86 co-accessed register
+ * Call this routine before access SMIx98 & SMIxA8
+ *
+ */
+VOID
+AcquirePspSmiRegMutex (
+  VOID
+  )
+{
+  UINT32 PspBarAddr;
+  UINT32 MutexReg0;
+  UINT32 MutexReg1;
+
+  PspBarAddr = 0;
+  if (GetPspBar3Addr (&PspBarAddr)) {
+    MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET;
+    MutexReg1 = PspBarAddr + PSP_MUTEX_REG1_OFFSET;
+    *(volatile UINT32*)(UINTN)(MutexReg0) |= BIT0;
+    *(volatile UINT32*)(UINTN)(MutexReg1) |= BIT0;
+    //Wait till PSP FW release the mutex
+    while ((*(volatile UINT32*)(UINTN)(MutexReg0)& BIT1) && (*(volatile UINT32*)(UINTN)(MutexReg1) & BIT0)) {
+      ;
+    }
+  }
+}
+/**
+ * Release the Mutex for access PSP,X86 co-accessed register
+ * Call this routine after access SMIx98 & SMIxA8
+ *
+ */
+VOID
+ReleasePspSmiRegMutex (
+  VOID
+  )
+{
+  UINT32 PspBarAddr;
+  UINT32 MutexReg0;
+
+  PspBarAddr = 0;
+  if (GetPspBar3Addr (&PspBarAddr)) {
+    MutexReg0 = PspBarAddr + PSP_MUTEX_REG0_OFFSET;
+    *(volatile UINT32*)(UINTN)(MutexReg0) &= ~BIT0;
+  }
+}
 
 /*---------------------------------------------------------------------------------------*/
 /**
@@ -461,4 +650,30 @@ PspLibPciIndirectWrite (
   LibAmdPciWrite (Width, Address, Value, NULL);
 }
 
+BOOLEAN
+IsS3Resume (
+  )
+{
+  UINT16                  AcpiPm1CntBlk;
+  UINT16                  SleepType;
+  UINT8                   PmioAddr;
+
+  AcpiPm1CntBlk = 0;
+  //Get AcpiPm1CntBlk address
+  //PMIO register can only allow 8bits access
+  PmioAddr = PMIO_REG62;
+  LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL);
+  LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, &AcpiPm1CntBlk, NULL);
+
+  PmioAddr++;
+  LibAmdIoWrite (AccessWidth8, PMIO_INDEX_PORT, &PmioAddr, NULL);
+  LibAmdIoRead (AccessWidth8, PMIO_DATA_PORT, ((UINT8 *) &AcpiPm1CntBlk) + 1, NULL);
+
+  //Get Sleep type
+  LibAmdIoRead (AccessWidth16, AcpiPm1CntBlk, &SleepType, NULL);
+  SleepType = SleepType & 0x1C00;
+  SleepType = ((SleepType >> 10) & 7);
+
+  return ((SleepType == 3) ? TRUE : FALSE);
+}
 
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h
index 611539644f..e7f5a47d8d 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspBaseLib.h
@@ -9,12 +9,12 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  PSP
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  *
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -53,7 +53,7 @@
 #define PSP_PCI_DEV        0x08    ///< PSP Device address
 #define PSP_PCI_FN         0x00    ///< PSP Fn address
 #define PSP_PCI_BDA        ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8))
-#define GET_PSP_PCI_ADDR (Offset)    MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset)
+#define GET_PSP_PCI_ADDR(Offset)    MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset)
 
 #define PSP_PCI_DEVID_REG           0x00    ///< DevId
 #define PSP_PCI_CMD_REG             0x04    ///< CmdReg
@@ -63,7 +63,7 @@
 #define PSP_PCI_EXTRAPCIHDR_REG     0x48    ///< Extra PCI Header Ctr
 #define PSP_PCI_HTMSICAP_REG        0x5C    ///<  HT MSI Capability
 
-#define PSP_MSR_PRIVATE_BLOCK_BAR   0xC00110A2 ///< PSP Private Block Base Address (PSP_ADDR)
+#define PSP_MSR_PRIVATE_BLOCK_BAR   0xC00110A2ul ///< PSP Private Block Base Address (PSP_ADDR)
 
 #define D8F0x44_PmNxtPtrW_MASK                                  0xff
 
@@ -102,6 +102,28 @@ typedef struct {
 
 
 
+#define PSP_SMM_COMMUNICATION_TYPE_S3SCRIPT       0x1     ///< PspCommunicationType for S3 script
+
+/// PSP communication structure for S3SCRIPT
+typedef struct {
+  UINT64    PspBar3PciAddr;       /// PCI address for PSP BAR3
+  UINT32    PspBar3Val;           /// PCI register value  for PSP BAR3
+  UINT64    Pspx48PciAddr;        /// PCI address for PSP Register 48
+  UINT32    Pspx48Val;            /// PCI register value  for PSP Register 48
+} PSP_SMM_COMMUNICATION_S3SCRIPT;
+
+/// Union for PSP_SMM_COMMUNICATE_DATA
+typedef union _PSP_SMM_COMMUNICATE_DATA {
+  PSP_SMM_COMMUNICATION_S3SCRIPT S3Script;      ///< S3Script
+} PSP_SMM_COMMUNICATE_DATA;
+
+/// PSP communication header
+typedef struct {
+  UINT32                       PspCommunicationType;         ///< Type of smm communication buffer
+  PSP_SMM_COMMUNICATE_DATA     Data;                      ///< Communication buffer
+} PSP_SMM_COMMUNICATION_BUFFER;
+
+
 UINT32
 PspLibPciReadConfig (
   IN  UINT32 Register
@@ -131,9 +153,20 @@ GetPspDirBase (
 
 BOOLEAN
 PSPEntryInfo (
-  IN      PSP_DIRECTORY_ENTRY_TYPE    EntryType,
-  IN OUT  UINT64                      *EntryAddress,
-  IN      UINT32                      *EntrySize
+  IN       PSP_DIRECTORY_ENTRY_TYPE    EntryType,
+  IN OUT   UINT64                      *EntryAddress,
+  IN OUT   UINT32                      *EntrySize
+  );
+
+BOOLEAN
+PspSoftWareFuseInfo (
+  IN OUT   UINTN                       *FuseSpiAddress,
+  IN OUT   UINT64                      *FuseValue
+  );
+
+VOID
+UpdataPspDirCheckSum (
+  IN OUT   PSP_DIRECTORY         *PspDir
   );
 
 BOOLEAN
@@ -161,6 +194,15 @@ GetPspBar3Addr (
   IN OUT   UINT32 *PspMmio
   );
 
+VOID
+AcquirePspSmiRegMutex (
+  VOID
+  );
+
+VOID
+ReleasePspSmiRegMutex (
+  VOID
+  );
 
 BOOLEAN
 GetPspMboxStatus (
@@ -169,7 +211,7 @@ GetPspMboxStatus (
 
 
 BOOLEAN
-PspBarInitEarly (VOID);
+PspBarInitEarly ();
 
 VOID
 PspLibPciIndirectRead (
@@ -187,12 +229,8 @@ PspLibPciIndirectWrite (
   IN      VOID          *Value
   );
 
-UINT8
-PspLibAccessWidth (
-  IN       ACCESS_WIDTH AccessWidth
-  );
-
 BOOLEAN
-IsS3Resume (VOID);
+IsS3Resume ();
+
 
 #endif // _AMD_LIB_H_
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h
index 193cc6506c..e3fdd8d115 100644
--- a/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h
+++ b/src/vendorcode/amd/pi/00670F00/Proc/Psp/PspBaseLib/PspDirectory.h
@@ -8,11 +8,11 @@
  * @xrefitem bom "File Content Label" "Release Content"
  * @e project:      AGESA
  * @e sub-project:  PSP
- * @e \$Revision: 309090 $   @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ * @e \$Revision$   @e \$Date$
  */
  /*****************************************************************************
  *
- * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -51,6 +51,7 @@ typedef struct _FIRMWARE_ENTRY_TABLE {
   UINT32  GecRomBase;   ///< Base Address for Gmc Firmware
   UINT32  XHCRomBase;   ///< Base Address for XHCI Firmware
   UINT32  PspDirBase;   ///< Base Address for PSP directory
+  UINT32  NewPspDirBase;   ///< Base Address of PSP directory from program start from ST
 } FIRMWARE_ENTRY_TABLE;
 
 /// Define structure for PSP directory
@@ -64,16 +65,32 @@ typedef struct {
 
 /// define various enum type for PSP entry type
 enum _PSP_DIRECTORY_ENTRY_TYPE {
-  AMD_PUBLIC_KEY                  = 0,    ///< PSP entry pointer to AMD public key
-  PSP_FW_BOOT_LOADER              = 1,    ///< PSP entry points to PSP boot loader in SPI space
-  PSP_FW_TRUSTED_OS               = 2,    ///< PSP entry points to PSP Firmware region in SPI space
-  PSP_FW_RECOVERY_BOOT_LOADER     = 3,    ///< PSP entry point to PSP recovery region.
-  PSP_NV_DATA                     = 4,    ///< PSP entry points to PSP data region in SPI space
-  BIOS_PUBLIC_KEY                 = 5,    ///< PSP entry points to BIOS public key stored in SPI space
-  BIOS_RTM_FIRMWARE               = 6,    ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space
-  BIOS_RTM_SIGNATURE              = 7,    ///< PSP entry points to signed BIOS RTM hash stored  in SPI space
-  SMU_OFFCHIP_FW                  = 8     ///< PSP entry points to SMU image
+  AMD_PUBLIC_KEY                  = 0x00,           ///< PSP entry pointer to AMD public key
+  PSP_FW_BOOT_LOADER              = 0x01,           ///< PSP entry points to PSP boot loader in SPI space
+  PSP_FW_TRUSTED_OS               = 0x02,           ///< PSP entry points to PSP Firmware region in SPI space
+  PSP_FW_RECOVERY_BOOT_LOADER     = 0x03,           ///< PSP entry point to PSP recovery region.
+  PSP_NV_DATA                     = 0x04,           ///< PSP entry points to PSP data region in SPI space
+  BIOS_PUBLIC_KEY                 = 0x05,           ///< PSP entry points to BIOS public key stored in SPI space
+  BIOS_RTM_FIRMWARE               = 0x06,           ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space
+  BIOS_RTM_SIGNATURE              = 0x07,           ///< PSP entry points to signed BIOS RTM hash stored  in SPI space
+  SMU_OFFCHIP_FW                  = 0x08,           ///< PSP entry points to SMU image
+  AMD_SEC_DBG_PUBLIC_KEY          = 0x09,           ///< PSP entry pointer to Secure Unlock Public key
+  OEM_PSP_FW_PUBLIC_KEY           = 0x0A,           ///< PSP entry pointer to an optional public part of the OEM PSP Firmware Signing Key Token
+  AMD_SOFT_FUSE_CHAIN_01          = 0x0B,           ///< PSP entry pointer to 64bit PSP Soft Fuse Chain
+  PSP_BOOT_TIME_TRUSTLETS         = 0x0C,           ///< PSP entry points to boot-loaded trustlet binaries
+  PSP_BOOT_TIME_TRUSTLETS_KEY     = 0x0D,           ///< PSP entry points to key of the boot-loaded trustlet binaries
+  PSP_AGESA_RESUME_FW             = 0x10,           ///< PSP Entry points to PSP Agesa-Resume-Firmware
+  SMU_OFF_CHIP_FW_2               = 0x12,           ///< PSP entry points to secondary SMU image
+  PSP_S3_NV_DATA                  = 0x1A,           ///< PSP entry pointer to S3 Data Blob
+  AMD_SCS_BINARY                  = 0x5F,           ///< Software Configuration Settings Data Block
 };
+
+#define PSP_ENTRY_PROGRAM_ID_0             0                  ///< Program identifier 0, used when two programs share the same root key
+#define PSP_ENTRY_PROGRAM_ID_1             1                  ///< Program identifier 1, used when two programs share the same root key
+
+#define PSP_ENTRY_CZ_PROGRAM_ID            PSP_ENTRY_PROGRAM_ID_0       ///< CZ Program identifier
+#define PSP_ENTRY_BR_PROGRAM_ID            PSP_ENTRY_PROGRAM_ID_1       ///< BR Program identifier
+
 typedef UINT32 PSP_DIRECTORY_ENTRY_TYPE;
 
 /// Structure for PSP Entry