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authorAaron Durbin <adurbin@chromium.org>2017-12-12 14:56:41 -0700
committerAaron Durbin <adurbin@chromium.org>2017-12-13 15:53:24 +0000
commit02b43aa2e01772556a6b18a40677bb2438ba8327 (patch)
treef1c6a9904f76615d4cf2d0367d4dc3cab2736aca /src/vendorcode/amd
parentec5a947b44f1f2bd2bd90071df2617de608cd1c2 (diff)
downloadcoreboot-02b43aa2e01772556a6b18a40677bb2438ba8327.tar.xz
vc/amd/pi/0067F00: add option to add AGESA binary PI as stage
Stage addition to CBFS allows relocation to happen on the fly. Take advantage of that by adding AGESA binary PI as a stage file so that each instance will be relocated properly within CBFS. Without this patch Chrome OS having multiple CBFS instances just redirects the AGESA calls back into RO which is inappropriate. BUG=b:65442265,b:68141063 TEST=Enabled AGESA_BINARY_PI_AS_STAGE and used ELF file. Booted and noted each instance in Chrome OS build was relocated. Change-Id: Ic0141bc6436a30f855148ff205f28ac9bce30043 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/vendorcode/amd')
-rw-r--r--src/vendorcode/amd/pi/00670F00/Makefile.inc8
-rw-r--r--src/vendorcode/amd/pi/Kconfig10
2 files changed, 18 insertions, 0 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc
index a5e644e78c..f1e340e751 100644
--- a/src/vendorcode/amd/pi/00670F00/Makefile.inc
+++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc
@@ -125,7 +125,15 @@ ramstage-libs += $(agesa_output_path)/libagesa.a
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME)
$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE)
+ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y)
+$(CONFIG_AGESA_CBFS_NAME)-type := stage
+$(CONFIG_AGESA_CBFS_NAME)-options := --xip
+# 4KiB alignment to handle any interior alignment. Current AGESA only has
+# 64 byte alignment.
+$(CONFIG_AGESA_CBFS_NAME)-align := 4096
+else
$(CONFIG_AGESA_CBFS_NAME)-type := raw
$(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION)
+endif
endif
diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig
index 3743d07580..8c38a790ea 100644
--- a/src/vendorcode/amd/pi/Kconfig
+++ b/src/vendorcode/amd/pi/Kconfig
@@ -49,6 +49,15 @@ config AGESA_BINARY_PI_FILE
help
Specify the binary file to use for AMD platform initialization.
+config AGESA_BINARY_PI_AS_STAGE
+ bool "AGESA Binary PI is added as stage to CBFS."
+ depends on SOC_AMD_STONEYRIDGE_FT4 || SOC_AMD_STONEYRIDGE_FP4
+ help
+ AGESA will be added as a stage utilizing --xip cbfstool options
+ as needed relocating the image to the proper location in memory-mapped
+ cpu address space. It's required that the file be in ELF format
+ containing the relocations necessary for relocating at runtime.
+
config AGESA_CBFS_NAME
string
default "AGESA"
@@ -56,6 +65,7 @@ config AGESA_CBFS_NAME
config AGESA_BINARY_PI_LOCATION
hex "AGESA PI binary address in ROM"
default 0xFFE00000
+ depends on !AGESA_BINARY_PI_AS_STAGE
help
Specify the ROM address at which to store the binary Platform
Initialization code.