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| author | Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> | 2021-04-22 05:00:32 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-04-26 08:28:22 +0000 |
| commit | 250e610fa082473b3592d06c69316ec1daa88116 (patch) | |
| tree | ecdded88b81b30c251520b9983ab4abc1df1fabb /src/vendorcode/amd | |
| parent | b1e8a8a6cee3e67962ecb03afd84aabb391ff9a8 (diff) | |
| download | coreboot-250e610fa082473b3592d06c69316ec1daa88116.tar.xz | |
vc/amd/fsp/cezanne:Add s0i_enable upd control
Add upd to enable S0i3 in fsp.
BUG=b:178728116
TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the
sleep state configuration from the mainboard.
Cq-Depend: chrome-internal:3777391
Change-Id: I01759caa4d72e284b2b960634f89c6a2ab1dad57
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/fsp/cezanne/FspmUpd.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index 66c8ab81b4..dd59d52ac6 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -100,7 +100,8 @@ typedef struct __packed { /** Offset 0x04A4**/ uint8_t fch_ioapic_id; /** Offset 0x04A5**/ uint8_t sata_enable; /** Offset 0x04A6**/ uint8_t fch_reserved[32]; - /** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[58]; + /** Offset 0x04A7**/ uint8_t s0i3_enable; + /** Offset 0x04C6**/ uint8_t UnusedUpdSpace0[57]; /** Offset 0x0500**/ uint16_t UpdTerminator; } FSP_M_CONFIG; |