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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-07-08 09:22:13 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-03 00:05:52 +0000 |
| commit | 48a6c018bcb8a182c4934d2788567e512d490f96 (patch) | |
| tree | 59ecbc8962d7fa937ae8ebff140e8df970267d5f /src/vendorcode/amd | |
| parent | d477565dbd6e9b6467f49c84a4f05047ffa22682 (diff) | |
| download | coreboot-48a6c018bcb8a182c4934d2788567e512d490f96.tar.xz | |
src: Remove redundant use of ACPI offset(0)
IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl | 2 | ||||
| -rw-r--r-- | src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl index 463093c6b1..5d545b189b 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibCore.esl @@ -142,7 +142,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } return (varPciReg32) @@ -160,7 +159,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } Store (Arg2, varPciReg32) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl index 9dba662995..342c646db5 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieAlibV1/PcieAlibPciLib.esl @@ -55,7 +55,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } return (varPciReg32) @@ -73,7 +72,6 @@ Add (Arg1, Local0, Local0) OperationRegion(varOperationRegionMmio, SystemMemory, Local0, 0x4) Field(varOperationRegionMmio, DWordAcc, NoLock, Preserve) { - Offset (0x0), varPciReg32, 32, } Store (Arg2, varPciReg32) |