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| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-07-25 18:46:46 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-07-27 21:31:04 +0000 |
| commit | 9df969aebfdeb6d162cd2aeb288fa4420a21953a (patch) | |
| tree | c7e79f7dec871870b7e865570a706092a6541f0d /src/vendorcode/amd | |
| parent | c95d6ffa7cd532243210723e43b977aa880a72e8 (diff) | |
| download | coreboot-9df969aebfdeb6d162cd2aeb288fa4420a21953a.tar.xz | |
soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCK
Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/pi/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index cadccdc371..962f0fc0d2 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -146,6 +146,7 @@ $(obj)/agesa/libagesa.a: $(call src-to-obj,libagesa,$(agesa_src_files)) @printf " AGESA $(subst $(obj)/,,$(@))\n" ar rcs $@ $+ +bootblock-libs += $(obj)/agesa/libagesa.a romstage-libs += $(obj)/agesa/libagesa.a ramstage-libs += $(obj)/agesa/libagesa.a |