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author | Alexandru Gagniuc <alexandrux.gagniuc@intel.com> | 2016-04-06 10:49:55 -0700 |
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committer | Aaron Durbin <adurbin@chromium.org> | 2016-05-12 04:54:30 +0200 |
commit | 717dccc3ee7d7f2f25386476b5ef30d8ce3effa4 (patch) | |
tree | f903b4bbb672832df3caf9130e0280efd790aa99 /src/vendorcode/amd | |
parent | c364019486bbdf960d1b217bb87f8ccbb59bc591 (diff) | |
download | coreboot-717dccc3ee7d7f2f25386476b5ef30d8ce3effa4.tar.xz |
soc/apollolake: Handle non-standard ACPI BAR in PMC device
The ACPI BAR (BAR2 - offset 0x20) is not PCI compliant. That means
that probing may not work. In that case, a resource still needs to be
created for the BAR.
BONUS: We now avoid the need to declare the MMIO resources as fixed.
Change-Id: I52fd2d2718ac8013067aaa450c5eb31e00738ab9
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/14634
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/amd')
0 files changed, 0 insertions, 0 deletions