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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-20 15:46:56 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-23 13:46:40 +0000 |
| commit | a19d98647b0b1862c28b362505b30f4551b2fe2c (patch) | |
| tree | 48c2975b0cd46c5933156b9f334babf10d1bf8ff /src/vendorcode/amd | |
| parent | a2b04f45c0f8383cf8d6f5ea513d1598c23e822c (diff) | |
| download | coreboot-a19d98647b0b1862c28b362505b30f4551b2fe2c.tar.xz | |
vc/amd/fsp/picasso: add logical to lane number in port descriptor struct
The lane numbers in the PCIe/DXIO descriptor are the logical and not the
physical ones, so add logical to the corresponding field names of the
fsp_pcie_descriptor struct.
Change-Id: I7037fed225119218e87593932815aff815e83ff8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/amd')
| -rw-r--r-- | src/vendorcode/amd/fsp/picasso/platform_descriptors.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index 9765ea6f2e..acf821b6e2 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -113,8 +113,8 @@ typedef struct __packed { /* Beware that the lane numbers in here are the logical and not the physical lane numbers! */ typedef struct __packed { uint8_t engine_type; - uint8_t start_lane; // Start lane of the pci device - uint8_t end_lane; // End lane of the pci device + uint8_t start_logical_lane; // Start lane of the pci device + uint8_t end_logical_lane; // End lane of the pci device uint8_t gpio_group_id; // FCH reset number. 0 is global reset uint32_t port_present :1; // Should be TRUE if train link uint32_t reserved_3 :7; |