vendorcode/amd/pi: Tidy up gcccar.inc

Remove register preservations that are not required and
fix comments about register usage accordingly.

Change-Id: Ibc9ed982ac55e947c100739250db122033348a82
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20576
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

4 files changed, 20 insertions, 72 deletions

diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index 11376d50c7..4092dbf971 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -1164,7 +1164,7 @@ node_core_f15_exit:
 * AMD_ENABLE_STACK:  Setup a stack
 *
 *   In:
-*       EBX  = Return address (preserved)
+*       No inputs
 *
 *   Out:
 *       SS:ESP - Our new private stack location
@@ -1175,11 +1175,8 @@ node_core_f15_exit:
 *
 *   Requirements:
 *       * This routine presently is limited to a max of 64 processor cores
-*   Preserved:
-*       ebx ebp
 *   Destroyed:
-*       eax, ecx, edx, edi, esi, ds, es, ss, esp
-*       mmx0, mmx1
+*       EBX, EDX, EDI, ESI, EBP, DS, ES
 *
 *   Description:
 * Fixed MTRR address allocation to cores:
@@ -1239,8 +1236,6 @@ node_core_f15_exit:
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
 #   of its limited lifetime, it will not conflict with typical PCI devices.
-    movd    %ebx, %mm0                    # Put return address in a safe place
-    movd    %ebp, %mm1                    # Save some other user registers
 
     # get node id and core id of current executing core
     GET_NODE_ID_CORE_ID                 # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
@@ -1554,9 +1549,6 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
         or      $0x40000000, %eax          # eax = AGESA_WARNING (Stack has already been set up)
     #.endif
     0:
-
-    movd        %mm0, %ebx                # Restore return address
-    movd        %mm1, %ebp
 .endm
 
 /*****************************************************************************
@@ -1576,17 +1568,15 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 *       none
 *
 *   Out:
-*       EAX = AGESA_SUCCESS
+*       none
 *
 *   Preserved:
-*       ebx
+*       ESP
 *   Destroyed:
-*       eax, ecx, edx, esp
+*       EAX, EBX, ECX, EDX, EDI, ESI
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK
 
-    mov     %ebx, %esp                    # Save return address
-
     # get node/core/flags of current executing core
     GET_NODE_ID_CORE_ID                 # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
 
@@ -1612,8 +1602,5 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 
     AMD_DISABLE_STACK_FAMILY_HOOK       # Re-Enable 'normal' cache operations
 
-    mov     %esp, %ebx
-    xor     %eax, %eax
-
 .endm
 
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
index 9badccfcd5..8d208d6521 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -900,7 +900,7 @@ node_core_f15_exit:
 * AMD_ENABLE_STACK:  Setup a stack
 *
 *   In:
-*       EBX  = Return address (preserved)
+*       No inputs
 *
 *   Out:
 *       SS:ESP - Our new private stack location
@@ -911,11 +911,8 @@ node_core_f15_exit:
 *
 *   Requirements:
 *       * This routine presently is limited to a max of 64 processor cores
-*   Preserved:
-*       ebx ebp
 *   Destroyed:
-*       eax, ecx, edx, edi, esi, ds, es, ss, esp
-*       mmx0, mmx1
+*       EBX, EDX, EDI, ESI, EBP, DS, ES
 *
 *   Description:
 * Fixed MTRR address allocation to cores:
@@ -975,8 +972,6 @@ node_core_f15_exit:
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
 #   of its limited lifetime, it will not conflict with typical PCI devices.
-    movd    %ebx, %mm0                    # Put return address in a safe place
-    movd    %ebp, %mm1                    # Save some other user registers
 
     # get node id and core id of current executing core
     GET_NODE_ID_CORE_ID                 # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
@@ -1293,9 +1288,6 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
         or      $0x40000000, %eax          # eax = AGESA_WARNING (Stack has already been set up)
     #.endif
     0:
-
-    movd        %mm0, %ebx                # Restore return address
-    movd        %mm1, %ebp
 .endm
 
 /*****************************************************************************
@@ -1315,17 +1307,15 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 *       none
 *
 *   Out:
-*       EAX = AGESA_SUCCESS
+*       none
 *
 *   Preserved:
-*       ebx
+*       ESP
 *   Destroyed:
-*       eax, ecx, edx, esp
+*       EAX, EBX, ECX, EDX, EDI, ESI
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK
 
-    mov     %ebx, %esp                    # Save return address
-
     # get node/core/flags of current executing core
     GET_NODE_ID_CORE_ID                 # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
 #1:	 jmp 1b
@@ -1351,8 +1341,5 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 
     AMD_DISABLE_STACK_FAMILY_HOOK       # Re-Enable 'normal' cache operations
 
-    mov     %esp, %ebx
-    xor     %eax, %eax
-
 .endm
 
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index 1dd0724464..92fd7e24fb 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -898,7 +898,7 @@ node_core_f15_exit:
 * AMD_ENABLE_STACK:  Setup a stack
 *
 *   In:
-*       EBX  = Return address (preserved)
+*       No inputs
 *
 *   Out:
 *       SS:ESP - Our new private stack location
@@ -909,11 +909,8 @@ node_core_f15_exit:
 *
 *   Requirements:
 *       * This routine presently is limited to a max of 64 processor cores
-*   Preserved:
-*       ebx ebp
 *   Destroyed:
-*       eax, ecx, edx, edi, esi, ds, es, ss, esp
-*       mmx0, mmx1
+*       EBX, EDX, EDI, ESI, EBP, DS, ES
 *
 *   Description:
 * Fixed MTRR address allocation to cores:
@@ -973,8 +970,6 @@ node_core_f15_exit:
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
 #   of its limited lifetime, it will not conflict with typical PCI devices.
-    movd    %ebx, %mm0                    # Put return address in a safe place
-    movd    %ebp, %mm1                    # Save some other user registers
 
     # get node id and core id of current executing core
     GET_NODE_ID_CORE_ID                 # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
@@ -1291,9 +1286,6 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
         or      $0x40000000, %eax          # eax = AGESA_WARNING (Stack has already been set up)
     #.endif
     0:
-
-    movd        %mm0, %ebx                # Restore return address
-    movd        %mm1, %ebp
 .endm
 
 /*****************************************************************************
@@ -1313,17 +1305,15 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 *       none
 *
 *   Out:
-*       EAX = AGESA_SUCCESS
+*       none
 *
 *   Preserved:
-*       ebx
+*       ESP
 *   Destroyed:
-*       eax, ecx, edx, esp
+*       EAX, EBX, ECX, EDX, EDI, ESI
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK
 
-    mov     %ebx, %esp                    # Save return address
-
     # get node/core/flags of current executing core
     GET_NODE_ID_CORE_ID                 # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
 #1:	 jmp 1b
@@ -1349,8 +1339,5 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 
     AMD_DISABLE_STACK_FAMILY_HOOK       # Re-Enable 'normal' cache operations
 
-    mov     %esp, %ebx
-    xor     %eax, %eax
-
 .endm
 
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index 1ad87c74f3..4761e48231 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -879,7 +879,7 @@ node_core_f16_exit:
 * AMD_ENABLE_STACK:  Setup a stack
 *
 *   In:
-*       EBX  = Return address (preserved)
+*       No inputs
 *
 *   Out:
 *       SS:ESP - Our new private stack location
@@ -890,11 +890,8 @@ node_core_f16_exit:
 *
 *   Requirements:
 *       * This routine presently is limited to a max of 64 processor cores
-*   Preserved:
-*       ebx ebp
 *   Destroyed:
-*       eax, ecx, edx, edi, esi, ds, es, ss, esp
-*       mmx0, mmx1
+*       EBX, EDX, EDI, ESI, EBP, DS, ES
 *
 *   Description:
 * Fixed MTRR address allocation to cores:
@@ -954,8 +951,6 @@ node_core_f16_exit:
 #   Note that SS:ESP will be default stack.  Note that this stack
 #   routine will not be used after memory has been initialized.  Because
 #   of its limited lifetime, it will not conflict with typical PCI devices.
-    movd    %ebx, %mm0                    # Put return address in a safe place
-    movd    %ebp, %mm1                    # Save some other user registers
 
     # get node id and core id of current executing core
     GET_NODE_ID_CORE_ID                 # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
@@ -1267,9 +1262,6 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
         or      $0x40000000, %eax          # eax = AGESA_WARNING (Stack has already been set up)
     #.endif
     0:
-
-    movd        %mm0, %ebx                # Restore return address
-    movd        %mm1, %ebp
 .endm
 
 /*****************************************************************************
@@ -1289,17 +1281,15 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 *       none
 *
 *   Out:
-*       EAX = AGESA_SUCCESS
+*       none
 *
 *   Preserved:
-*       ebx
+*       ESP
 *   Destroyed:
-*       eax, ecx, edx, esp
+*       EAX, EBX, ECX, EDX, EDI, ESI
 *****************************************************************************/
 .macro  AMD_DISABLE_STACK
 
-    mov     %ebx, %esp                    # Save return address
-
     # get node/core/flags of current executing core
     GET_NODE_ID_CORE_ID                 # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
 
@@ -1325,8 +1315,5 @@ ClearTheStack:                          # Stack base is in SS, stack pointer is
 
     AMD_DISABLE_STACK_FAMILY_HOOK       # Re-Enable 'normal' cache operations
 
-    mov     %esp, %ebx
-    xor     %eax, %eax
-
 .endm