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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-24 08:09:40 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-27 13:50:39 +0200 |
| commit | 5f4b4c42964445d1bc517c461090f17655e84131 (patch) | |
| tree | 30361070840ded66d75a52e6e1362c45b66979db /src/vendorcode/amd | |
| parent | ae738acdc5f02d232e035538c67d63ba19b9ccaa (diff) | |
| download | coreboot-5f4b4c42964445d1bc517c461090f17655e84131.tar.xz | |
arch/x86: Add bootblock and postcar support for SOC MTRR access
Quark does not support the rdmsr and wrmsr instructions. Use SOC
specific routines to configure the MTRRs on Quark based platforms.
Add cpu_common.c as a build dependency to provide access to the routine
cpu_phys_address_size.
TEST=Build and run on Galileo Gen2
Change-Id: I43b7067c66c5c55b42097937e862078adf17fb19
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15846
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/amd')
0 files changed, 0 insertions, 0 deletions