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authorMartin Roth <martinroth@google.com>2017-06-03 20:03:18 -0600
committerPatrick Georgi <pgeorgi@google.com>2017-06-07 12:09:15 +0200
commite18e6427d0f3261f9ec361d4418b8fe1dd7cc469 (patch)
treef6a10fc93dddada7e49108a5ad06e71590f2d54c /src/vendorcode/amd
parente81ce0483db982c741eebdda649111eee22a853b (diff)
downloadcoreboot-e18e6427d0f3261f9ec361d4418b8fe1dd7cc469.tar.xz
src: change coreboot to lowercase
The word 'coreboot' should always be written in lowercase, even at the start of a sentence. Change-Id: I7945ddb988262e7483da4e623cedf972380e65a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20029 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/vendorcode/amd')
-rw-r--r--src/vendorcode/amd/cimx/sb700/SBCMN.c2
-rw-r--r--src/vendorcode/amd/cimx/sb700/SBPort.c2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/amd/cimx/sb700/SBCMN.c b/src/vendorcode/amd/cimx/sb700/SBCMN.c
index 7d5b4f4a74..ca2ec782c6 100644
--- a/src/vendorcode/amd/cimx/sb700/SBCMN.c
+++ b/src/vendorcode/amd/cimx/sb700/SBCMN.c
@@ -145,7 +145,7 @@ void commonInitEarlyBoot(AMDSBCFG* pConfig) {
RWPMIO(SB_PMIO_REG65, AccWidthUint8 | S3_SAVE, ~(UINT32)BIT4, BIT4);
- #if 0 //KZ [083011]-It's used wrong BIOS SIZE for Coreboot.
+ #if 0 //KZ [083011]-It's used wrong BIOS SIZE for coreboot.
//For being compatible with earlier revision, check whether ROM decoding is changed already outside CIMx before
//changing it.
ReadPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG68, AccWidthUint16 | S3_SAVE, &dwTempVar);
diff --git a/src/vendorcode/amd/cimx/sb700/SBPort.c b/src/vendorcode/amd/cimx/sb700/SBPort.c
index 6c5740bf37..d1484812b9 100644
--- a/src/vendorcode/amd/cimx/sb700/SBPort.c
+++ b/src/vendorcode/amd/cimx/sb700/SBPort.c
@@ -222,7 +222,7 @@ void sbPowerOnInit (AMDSBCFG *pConfig){
if (dbVar0 > 4) {
dbVar0 = 0;
}
- //KZ [061811]-It's used wrong BIOS SIZE for Coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
+ //KZ [061811]-It's used wrong BIOS SIZE for coreboot. RWPCI((LPC_BUS_DEV_FUN << 16) + SB_LPC_REG6C, AccWidthUint8 | S3_SAVE, 0x00, 0xF8 << dbVar0);
if (pConfig->Spi33Mhz)
//spi reg0c[13:12] to 01h to run spi 33Mhz in system bios