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authorKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-02 16:41:43 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2017-09-26 10:05:48 +0000
commit63fac81fc80d701a785ed61a3b5738ea0a821169 (patch)
tree7b50798c95fc1e3ec309351157197784e04131f8 /src/vendorcode/amd
parent8bf978c2aa92aa194d74e6588344f579de5828de (diff)
downloadcoreboot-63fac81fc80d701a785ed61a3b5738ea0a821169.tar.xz
AGESA: Implement POSTCAR_STAGE
Move all boards that have moved away from AGESA_LEGACY_WRAPPER or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE. We use POSTCAR_STAGE as a conditional in CAR teardown to tell our MTRR setup is prepared such that invalidation without writeback is a valid operation. Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/amd')
-rw-r--r--src/vendorcode/amd/agesa/f12/gcccar.inc4
-rw-r--r--src/vendorcode/amd/agesa/f14/gcccar.inc4
-rw-r--r--src/vendorcode/amd/agesa/f15/gcccar.inc4
-rw-r--r--src/vendorcode/amd/agesa/f15tn/gcccar.inc4
-rw-r--r--src/vendorcode/amd/agesa/f16kb/gcccar.inc4
-rw-r--r--src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc4
-rw-r--r--src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc4
-rw-r--r--src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc4
-rw-r--r--src/vendorcode/amd/pi/Makefile.inc2
9 files changed, 34 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc
index 6a81fc7add..c08c9f1291 100644
--- a/src/vendorcode/amd/agesa/f12/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f12/gcccar.inc
@@ -678,7 +678,11 @@ fam12_enable_stack_hook_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
+#else
+ invd
+#endif
mov %bx, %ax # Restore INVD -> WBINVD bit
_WRMSR
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 10214a8f03..678990f5b6 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -826,7 +826,11 @@ fam14_enable_stack_hook_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
+#else
+ invd
+#endif
bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
_WRMSR
diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc
index 427c7e5622..5076272e11 100644
--- a/src/vendorcode/amd/agesa/f15/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15/gcccar.inc
@@ -433,7 +433,11 @@ fam10_enable_stack_hook_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
+#else
+ invd
+#endif
mov %bx, %ax # Restore INVD -> WBINVD bit
_WRMSR
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index 7ac9613fca..8e15503551 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -1263,7 +1263,11 @@ fam15_disable_stack_remote_read_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
+#else
+ invd
+#endif
#.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
cmp $01, %bh
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index 26e61da34b..8ad4d1ddc4 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -615,7 +615,11 @@ fam16_disable_stack_remote_read_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
+#else
+ invd
+#endif
#Do Standard Family 16 work
mov $HWCR, %ecx # MSR:C001_0015h
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index 4092dbf971..fc7d0e461f 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -916,7 +916,11 @@ fam15_disable_stack_remote_read_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
+#else
+ invd
+#endif
#.if (bh == 01h) || (bh == 03h) ; Is this TN or KV?
cmp $01, %bh
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
index 8d208d6521..45ed2948e7 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -651,7 +651,11 @@ fam15_disable_stack_remote_read_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
+#else
+ invd
+#endif
# #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
# cmp $01, %bh
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index 4761e48231..5a4f7b9290 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -615,7 +615,11 @@ fam16_disable_stack_remote_read_exit:
# This shouldn't be used with S3 resume IF the stack/cache area is
# not reserved and over system memory.
#--------------------------------------------------------------------------
+#if !IS_ENABLED(CONFIG_POSTCAR_STAGE)
wbinvd
+#else
+ invd
+#endif
#Do Standard Family 16 work
mov $HWCR, %ecx # MSR:C001_0015h
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index bcf078deee..0192faad4a 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -85,7 +85,9 @@ export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
+CC_postcar:= $(CC_postcar) -I$(AGESA_ROOT)/binaryPI
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
+
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_64 := $(CC_x86_64) $(AGESA_INC) $(AGESA_CFLAGS)