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authorKarthikeyan Ramasubramanian <kramasub@google.com>2020-08-20 16:04:58 -0600
committerEdward O'Callaghan <quasisec@chromium.org>2020-08-22 00:31:34 +0000
commitb9042cb942528a056e3a6aacebcede76ce3f15a6 (patch)
tree2910961684590b889e7f96f08c49d00f88697154 /src/vendorcode/google/chromeos/Makefile.inc
parent7b58f9413db21b0fc71e65a99e43f699e83ea0f9 (diff)
downloadcoreboot-b9042cb942528a056e3a6aacebcede76ce3f15a6.tar.xz
vendorcode/google/chromeos: Introduce helper for CSE board reset
When CSE Lite jumps from RO to RW, certain boards need to request Embedded Controller (EC) to trigger cold reset of SoC. This change introduces a helper to override the default global reset. BUG=None TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is triggered when cr50 is running firmware versions newer than 0.0.22. On cr50 versions 0.0.22 or older, EC triggers cold reset of AP. Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Diffstat (limited to 'src/vendorcode/google/chromeos/Makefile.inc')
-rw-r--r--src/vendorcode/google/chromeos/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index a25700f8bb..b429d6b14a 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -10,6 +10,7 @@ ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c
ramstage-$(CONFIG_USE_SAR) += sar.c
ramstage-$(CONFIG_CHROMEOS_DSM_CALIB) += dsm_calib.c
ramstage-$(CONFIG_TPM_CR50) += cr50_enable_update.c
+ramstage-$(CONFIG_CHROMEOS_CSE_BOARD_RESET_OVERRIDE) += cse_board_reset.c
bootblock-y += watchdog.c
verstage-y += watchdog.c