diff options
| author | Duncan Laurie <dlaurie@google.com> | 2019-03-01 15:11:30 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-04 14:04:46 +0000 |
| commit | cf8094cabbe517b2cced84e22a37ca3a8bcc7910 (patch) | |
| tree | 15638a4da34e6af23dd7476b473209f1cfc89496 /src/vendorcode/google/chromeos/gnvs.h | |
| parent | e0a0c63e098db215e73d20307fe1b3190ef32891 (diff) | |
| download | coreboot-cf8094cabbe517b2cced84e22a37ca3a8bcc7910.tar.xz | |
vendorcode/google/chromeos: Save VPD region into GNVS
Store the memory address of VPD region start and length for the memory
mapped RO_VPD and RW_VPD into GNVS so they can be used by ACPI code.
BUG=b:123925776
TEST=boot on sarien and verify VPD start/length in GNVS
Change-Id: I39073a9d78f5ff60bfe088860c087a5167f05fdf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/vendorcode/google/chromeos/gnvs.h')
| -rw-r--r-- | src/vendorcode/google/chromeos/gnvs.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 76ca20c294..b114dd0d68 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -70,7 +70,11 @@ typedef struct { u32 mehh[8]; // d9e management engine hash u32 ramoops_base; // dbe ramoops base address u32 ramoops_len; // dc2 ramoops length - u8 pad[314]; // dc6-eff + u32 vpd_ro_base; // dc6 pointer to RO_VPD + u32 vpd_ro_size; // dca size of RO_VPD + u32 vpd_rw_base; // dce pointer to RW_VPD + u32 vpd_rw_size; // dd2 size of RW_VPD + u8 pad[298]; // dd6-eff } __packed chromeos_acpi_t; void chromeos_init_chromeos_acpi(chromeos_acpi_t *init); |