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authorLin Huang <hl@rock-chips.com>2016-06-28 11:10:54 +0800
committerMartin Roth <martinroth@google.com>2016-07-12 00:27:08 +0200
commite3d78b82a76c6069a8111b278d4af57e9788ef9e (patch)
tree00337e51b9a8fddcc6db38ee8dd15536a5b534a6 /src/vendorcode/google/chromeos/vboot2/secdata_mock.c
parent9e624fc27f123c8b5eb6ef5a1ecd57facca16a7f (diff)
downloadcoreboot-e3d78b82a76c6069a8111b278d4af57e9788ef9e.tar.xz
rockchip/rk3399: calculate clocks based on parent clock speed
Currently aclkm pclkdbg atclk clocks use apll_l as a parent, but the apll_l frequency may change in firmware, so we need to caculate the div value based on the apll_l frequency. BRANCH=None BUG=chrome-os-partner:54376 TEST=Boot from Gru Change-Id: I2bd8886168453ce98efec58b5490c2430762769b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 116ae863a504630e2aff056564836d84198fcae2 Original-Change-Id: I7e3a5d9e3f608ddf15592d893117c92767fcd015 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/356397 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15581 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/vendorcode/google/chromeos/vboot2/secdata_mock.c')
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