summaryrefslogtreecommitdiff
path: root/src/vendorcode/google
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2013-03-26 13:34:37 -0500
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-03-29 20:10:14 +0100
commita09760eb451466c7972614ef9d73752e16a1bf69 (patch)
tree64a97a894065e2cd4fbc63882b65d35eb8313afa /src/vendorcode/google
parentbc07f5d93552640793254ce003937ec646120a21 (diff)
downloadcoreboot-a09760eb451466c7972614ef9d73752e16a1bf69.tar.xz
libpayload: add x86 ROM variable MTRR support
On x86, coreboot may allocate a variable range MTRR for enabling caching of the system ROM. Add the ability to parse this structure and add the result to the sysinfo structure. An example usage implementation would be to obtain the variable MTRR index that covers the ROM from the sysinfo structure. Then one would disable caching and change the MTRR type from uncacheable to write-protect and enable caching. The opposite sequence is required to tearn down the caching. Change-Id: I3bfe2028d8574d3adb1d85292abf8f1372cf97fa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2920 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/vendorcode/google')
0 files changed, 0 insertions, 0 deletions