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| author | Aaron Durbin <adurbin@chromium.org> | 2017-04-19 10:19:38 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-04-24 22:02:55 +0200 |
| commit | 8bc896f7129b8e47cbca1c15b87a449620186cf8 (patch) | |
| tree | 4310712849d51c4bd9082d07059c27dcd227c46e /src/vendorcode/google | |
| parent | fd053d74a3c14a90acbdfa290bd8c1f46ace5009 (diff) | |
| download | coreboot-8bc896f7129b8e47cbca1c15b87a449620186cf8.tar.xz | |
Kconfig: provide MAINBOARD_HAS_TPM_CR50 option
The CR50 TPM can do both SPI and I2C communication. However,
there's situations where policy needs to be applied for CR50
generically regardless of the I/O transport. Therefore add
MAINBOARD_HAS_TPM_CR50 to encompass that. Additionally,
once the mainboard has selected CR50 TPM automatically select
MAINBOARD_HAS_TPM2 since CR50 TPM is TPM 2.0.
Change-Id: I878f9b9dc99cfb0252d6fef7fc020fa3d391fcec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19370
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/vendorcode/google')
| -rw-r--r-- | src/vendorcode/google/chromeos/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index ab2478212d..1a4ac4fbbe 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -33,7 +33,7 @@ if CHROMEOS config CR50_IMMEDIATELY_COMMIT_FW_SECDATA bool - default y if MAINBOARD_HAS_I2C_TPM_CR50 || MAINBOARD_HAS_SPI_TPM_CR50 + default y if MAINBOARD_HAS_TPM_CR50 config CHROMEOS_RAMOOPS bool "Reserve space for Chrome OS ramoops" |