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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-11-09 17:39:39 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-11 21:08:56 +0000 |
| commit | 8e3b5e849cc4437486a33acb1ad4e4b7ce195989 (patch) | |
| tree | d82536085071ec5e89cfc77e9c81ffb2b0d9facd /src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h | |
| parent | 16995fb7eacf3a2b946795ab327c3c1764ab81ca (diff) | |
| download | coreboot-8e3b5e849cc4437486a33acb1ad4e4b7ce195989.tar.xz | |
intel/fsp: Update cannonlake FSP header
Update cannonlake FSP header to revision 7.x.11.43. Following changes
had been made:
1.Remove Minimum control ration from FSPM UPD.
2.Add Intersil VR command option in FSPS UPD.
3.Add minimum and maxiam ring ratio override.
TEST=None
Change-Id: I63c990e5766370a82dc1c044bcf744612229a605
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h index 24f0883588..665e5a090a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/MemInfoHob.h @@ -142,9 +142,15 @@ typedef struct { #ifndef MRC_DDR_TYPE_LPDDR3 #define MRC_DDR_TYPE_LPDDR3 2 #endif +#ifndef CPU_CFL//CNL +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#else//CFL #ifndef MRC_DDR_TYPE_UNKNOWN #define MRC_DDR_TYPE_UNKNOWN 3 #endif +#endif//CPU_CFL-endif #define MAX_PROFILE_NUM 4 // number of memory profiles supported #define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported |