diff options
| author | Jonathan Zhang <jonzhang@fb.com> | 2020-07-08 14:26:55 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-12 19:34:28 +0000 |
| commit | 0ccb3828bc6464dc51ef5075d9cc050272e0f75a (patch) | |
| tree | 7537e96bf2c50dee38c0a337c45cb7a2cd41e670 /src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h | |
| parent | bb50c672278c7ddee146b414e219ba45e8e0f559 (diff) | |
| download | coreboot-0ccb3828bc6464dc51ef5075d9cc050272e0f75a.tar.xz | |
vendocode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww28 release and adapt soc
CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX.
Also update IIO UDS HOB definition file accordingly.
Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG.
Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel
is that they will converge to use FSPM_CONFIG over time. So both will
co-exist for some time. Today coreboot common code expects FSP_M_CONFIG.
Accomodate this situation in FspmUpd.h.
The CPX-SP soc code is updated accordingly.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index 14e235f320..8dcac42bd3 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -155,6 +155,7 @@ typedef struct { uint8_t PcieSegment; UINT64_STRUCT SegMmcfgBase; uint16_t stackPresentBitmap; + uint16_t CxlPresentBitmap; uint16_t M2PciePresentBitmap; uint8_t TotM3Kti; uint8_t TotCha; @@ -199,20 +200,23 @@ typedef struct _STACK_RES { uint8_t Personality; // see STACK_TYPE for details uint8_t BusBase; uint8_t BusLimit; - uint16_t PciResourceIoBase; - uint16_t PciResourceIoLimit; - uint32_t IoApicBase; - uint32_t IoApicLimit; + uint16_t IoBase; // Base of IO configured for this stack + uint16_t IoLimit; // Limit of IO configured for this stack + uint32_t IoApicBase; // Base of IO configured for this stack + uint32_t IoApicLimit; // Limit of IO configured for this stack uint32_t Mmio32Base; uint32_t Mmio32Limit; uint64_t Mmio64Base; uint64_t Mmio64Limit; + uint8_t PciResourceBusBase; // Base of Bus resource available for PCI devices + uint8_t PciResourceBusLimit; // Limit of Bus resource available for PCI devices + uint16_t PciResourceIoBase; // Base of IO resource available for PCI devices + uint16_t PciResourceIoLimit; // Limit of IO resource available for PCI devices uint32_t PciResourceMem32Base; uint32_t PciResourceMem32Limit; uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Limit; uint32_t VtdBarAddress; - uint32_t Slt2HfiBarAddress; // KNH Only } STACK_RES; typedef struct { @@ -224,10 +228,10 @@ typedef struct { uint16_t PciResourceIoLimit; uint32_t IoApicBase; uint32_t IoApicLimit; - uint32_t PciResourceMem32Base; - uint32_t PciResourceMem32Limit; - uint64_t PciResourceMem64Base; - uint64_t PciResourceMem64Limit; + uint32_t Mmio32Base; + uint32_t Mmio32Limit; + uint64_t Mmio64Base; + uint64_t Mmio64Limit; STACK_RES StackRes[MAX_LOGIC_IIO_STACK]; uint32_t RcBaseAddress; IIO_DMI_PCIE_INFO PcieInfo; @@ -275,7 +279,6 @@ typedef struct { uint8_t DmiVc1; uint8_t DmiVcm; uint32_t CpuPCPSInfo; - uint8_t MctpEn; uint8_t cpuSubType; uint8_t SystemRasType; uint8_t numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC |