vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww24 release and adapt soc

The previous Intel CPX-SP FSP release was ww20 release.

The ww22 release fixs issues related to FSP_NV_STORAGE HOB. The end of end
flow of using memory training data to generate FSP_NV_STORAGE HOB and
using memory training data passed from bootloader to skip memory
training, works now. This saves 8 minutes of boot time (with FSP verbose
logging enabled on DeltaLake server).

This release also adds UPD parameters to support IIO bifuration.

The ww24 release has following updates:
a. Removed a number of unnecessary UPD parameters, such as mmiolSize,
mmiolBase, OemHookPostTopologyDiscovery, OemGetResourceMapUpdate.
b. Added UPD parameters to support PCIe ports configuration.
c. Updated IIO_UNIVERSAL_DATA HOB, each stack now has mmio base/limit
fields, in addition to PCIe resource memory base/limit fields.

With ww24 release, the issue with PCIe link training persists. On YV3
config A, the onboard NIC card has x4 connection to port 2D. This
NIC device is not recognized by FSP.

Corresponding soc/intel/xeon_sp/cpx change is made:
* There are changes in PLATFORM_DATA structure, so hob_display.c
is updated.
* There are changes in UPD parameters, so romstage.c is updated.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I70762b377a057d0fca7806f485cce8d479fb5baa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41903
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 8 insertions, 7 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
index 1ce5d3077a..14e235f320 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
@@ -203,6 +203,10 @@ typedef struct _STACK_RES {
   uint16_t                  PciResourceIoLimit;
   uint32_t                  IoApicBase;
   uint32_t                  IoApicLimit;
+  uint32_t                  Mmio32Base;
+  uint32_t                  Mmio32Limit;
+  uint64_t                  Mmio64Base;
+  uint64_t                  Mmio64Limit;
   uint32_t                  PciResourceMem32Base;
   uint32_t                  PciResourceMem32Limit;
   uint64_t                  PciResourceMem64Base;
@@ -233,10 +237,10 @@ typedef struct {
 typedef struct {
     uint16_t                  PlatGlobalIoBase;       // Global IO Base
     uint16_t                  PlatGlobalIoLimit;      // Global IO Limit
-    uint32_t                  PlatGlobalMmiolBase;    // Global Mmiol base
-    uint32_t                  PlatGlobalMmiolLimit;   // Global Mmiol limit
-    uint64_t                  PlatGlobalMmiohBase;    // Global Mmioh Base [43:0]
-    uint64_t                  PlatGlobalMmiohLimit;   // Global Mmioh Limit [43:0]
+    uint32_t                  PlatGlobalMmio32Base;    // Global Mmiol base
+    uint32_t                  PlatGlobalMmio32Limit;   // Global Mmiol limit
+    uint64_t                  PlatGlobalMmio64Base;    // Global Mmioh Base [43:0]
+    uint64_t                  PlatGlobalMmio64Limit;   // Global Mmioh Limit [43:0]
     QPI_CPU_DATA              CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU
     QPI_IIO_DATA              IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO
     uint32_t                  MemTsegSize;
@@ -256,10 +260,8 @@ typedef struct {
     uint32_t                  MmiolGranularity;
     UINT64_STRUCT             MmiohGranularity;
     uint8_t                   RemoteRequestThreshold;  //5370389
-    uint64_t                  softskuSocketPresentBitMap;    // bitmap of Softsku sockets with CPUs present detected
     uint32_t                  UboxMmioSize;
     uint32_t                  MaxAddressBits;
-    uint32_t                  DmiReservedMmiolSize[MAX_SOCKET];
 } PLATFORM_DATA;
 
 typedef struct {
@@ -273,7 +275,6 @@ typedef struct {
 	uint8_t                   DmiVc1;
 	uint8_t                   DmiVcm;
 	uint32_t                  CpuPCPSInfo;
-	uint8_t                   LtsxEnable;
 	uint8_t                   MctpEn;
 	uint8_t                   cpuSubType;
 	uint8_t                   SystemRasType;