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| author | Jonathan Zhang <jonzhang@fb.com> | 2020-10-01 14:20:41 -0700 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-08 12:04:45 +0000 |
| commit | 407d552e0c642da601a88283676ee885402e81c4 (patch) | |
| tree | eeef89028fa15250d0bba3f24a0384d4813573cb /src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h | |
| parent | 86b3bf10e60c137b01b81a37ce9827757f6af42d (diff) | |
| download | coreboot-407d552e0c642da601a88283676ee885402e81c4.tar.xz | |
vc/intel/fsp/fsp2_0/CPX-SP: update to Intel ww40 release
Intel CPX-SP FSP ww40 release adds MeUmaEnable FSP-M parameter,
and adds some fields to HOBs.
Update FspmUpd.h and HOB header files.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3d456be62a5feecdac267c1e8be52e2a25e8aac3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45940
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index db39c3be3c..9900a121f2 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -209,6 +209,7 @@ typedef struct _STACK_RES { uint64_t PciResourceMem64Base; uint64_t PciResourceMem64Limit; uint32_t VtdBarAddress; + uint32_t Mmio32MinSize; // Minimum required size of MMIO32 resource needed for this stack } STACK_RES; typedef struct { |