vendorcode/intel/fsp/fsp2_0/CPX-SP: update to ww34 release and adapt soc

Intel CPX-SP FSP ww34 release added some features:
a. change DDR frequency limit.
b. define MRC debug message verbosity level.
c. enable/disablee of PCH DCI.

In addition, there are some changes to HOB data structures.

Update UPD and HOB header files and adapt soc accordingly.

TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 2 insertions, 6 deletions

diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
index 8f9a91a0e9..79c41621c8 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h
@@ -188,18 +188,14 @@ typedef struct _STACK_RES {
   uint8_t                   Personality; // see STACK_TYPE for details
   uint8_t                   BusBase;
   uint8_t                   BusLimit;
-  uint16_t                  IoBase; // Base of IO configured for this stack
-  uint16_t                  IoLimit; // Limit of IO configured for this stack
+  uint16_t                  PciResourceIoBase;
+  uint16_t                  PciResourceIoLimit;
   uint32_t                  IoApicBase; // Base of IO configured for this stack
   uint32_t                  IoApicLimit; // Limit of IO configured for this stack
   uint32_t                  Mmio32Base;
   uint32_t                  Mmio32Limit;
   uint64_t                  Mmio64Base;
   uint64_t                  Mmio64Limit;
-  uint8_t                   PciResourceBusBase; // Base of Bus resource available for PCI devices
-  uint8_t                   PciResourceBusLimit; // Limit of Bus resource available for PCI devices
-  uint16_t                  PciResourceIoBase; // Base of IO resource available for PCI devices
-  uint16_t                  PciResourceIoLimit; // Limit of IO resource available for PCI devices
   uint32_t                  PciResourceMem32Base;
   uint32_t                  PciResourceMem32Limit;
   uint64_t                  PciResourceMem64Base;