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author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-09-28 14:10:06 -0700 |
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committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-09-30 01:15:44 +0200 |
commit | e1654235fd941b4a4cfb5f75325fe0a496a24c5f (patch) | |
tree | 1538f3c4ef350dc03d4fe323bcb5b94ac5c2df33 /src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h | |
parent | 127b5d1270fc3c7ea8be7c80670be8dcd9ea4147 (diff) | |
download | coreboot-e1654235fd941b4a4cfb5f75325fe0a496a24c5f.tar.xz |
mainboard/intel/quark: Add FSP selection values
Add Kconfig values to select the FSP setup:
* FSP version: 1.1 or 2.0
* Implementation: Subroutine or SEC/PEI core based
* Build type: DEBUG or RELEASE
* Enable all debugging for FSP
* Remove USE_FSP1_1 and USE_FSP2_0
Look for include files in vendorcode/intel/fsp/fsp???/quark
BRANCH=none
BUG=None
TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2
Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16806
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h')
-rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h | 93 |
1 files changed, 93 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h new file mode 100644 index 0000000000..02a1e09e7c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/quark/FsptUpd.h @@ -0,0 +1,93 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + +#pragma pack(push, 1) + + +/** Fsp T Common UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT8 Revision; + +/** Offset 0x0021 +**/ + UINT8 Reserved[3]; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0028 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x002C +**/ + UINT32 CodeRegionBase; + +/** Offset 0x0030 +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0034 +**/ + UINT8 Reserved1[12]; +} FSPT_COMMON_UPD; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_COMMON_UPD FsptCommonUpd; + +/** Offset 0x0040 +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack(pop) + +#endif |