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| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-01-23 23:26:02 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-25 10:42:23 +0000 |
| commit | 6d126acfac7ec8c13f9814c98d1016c64545cabd (patch) | |
| tree | a84847dd50ae1987e0970b8cf7f08cfdc6504bf5 /src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h | |
| parent | a8cb7ed784f51b071873585359257110c1bcc8be (diff) | |
| download | coreboot-6d126acfac7ec8c13f9814c98d1016c64545cabd.tar.xz | |
vendorcode/intel/fsp/fsp2_0/tgl: Update FSP header files for Tiger Lake
Update FSP header files for Tiger Lake platform version 2457.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I47574844a8b5fd888e8e75ed2f60f6df465b33ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 69f27b99e4..6cf3668fce 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2020, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -385,7 +385,7 @@ typedef struct { /** Offset 0x03FE - HECI3 state The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed. - 0: disable, 1: enable + DEPRECATED 0: disable, 1: enable $EN_DIS **/ UINT8 Heci3Enabled; |