diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-06-01 13:27:00 -0700 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2020-06-03 03:59:08 +0000 |
| commit | 9ff79c22808fb88a5d5cb184a439d26ce00ac15b (patch) | |
| tree | 10c600b2454c547d610758aefc5ef48457066955 /src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h | |
| parent | b763a4febcf7af67487cf2cf0038eebc61604a5a (diff) | |
| download | coreboot-9ff79c22808fb88a5d5cb184a439d26ce00ac15b.tar.xz | |
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3197
Update FSP headers for Tiger Lake platform generated based FSP
version 3197, which includes below additional UPDs:
FSPM:
CmdMirror
RMTBIT
FSPS:
SataPortsEnableDitoConfig
BUG=b:157725468
BRANCH=none
TEST=build and boot volteer
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I23d6baacc3d963b473280c7fdb1e5df950cd7ca8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41974
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h index 34f36898af..a68ba17bc6 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h @@ -727,7 +727,12 @@ typedef struct { /** Offset 0x085B - Reserved **/ - UINT8 Reserved40[50]; + UINT8 Reserved40[42]; + +/** Offset 0x0885 - Enable SATA Port Enable Dito Config + Enable DEVSLP Idle Timeout settings (DmVal, DitoVal). +**/ + UINT8 SataPortsEnableDitoConfig[8]; /** Offset 0x088D - Enable SATA Port DmVal DITO multiplier. Default is 15. @@ -879,7 +884,7 @@ typedef struct { /** Offset 0x0DB0 - Reserved **/ - UINT8 Reserved52[224]; + UINT8 Reserved52[232]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -894,11 +899,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0E90 +/** Offset 0x0E98 **/ UINT8 UnusedUpdSpace36[6]; -/** Offset 0x0E96 +/** Offset 0x0E9E **/ UINT16 UpdTerminator; } FSPS_UPD; |