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authorPatrick Georgi <pgeorgi@google.com>2018-09-13 11:48:43 -0400
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-10-12 23:20:53 +0000
commit6539e10c4f209ea4273a78528b26c1f9ff4a3047 (patch)
tree305cfa9247a93ccb0b3db13d644f46323859cdfd /src/vendorcode/intel/fsp
parentf3aa6e9319dc6eaabbb16eb3d09956711a121d30 (diff)
downloadcoreboot-6539e10c4f209ea4273a78528b26c1f9ff4a3047.tar.xz
drivers/intel/fsp2_0: Hook up IntelFSP repo
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using Intel's FSP repo (that we mirror) to build a complete BIOS ifd region with a simple coreboot build, automatically drawing in headers and binaries. This commit covers Apollolake, Coffeelake, Skylake, and Kabylake. Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's also supports Skylake. Another candidate (given 3rdparty/fsp's content) is Denverton NS, but it requires changes to coreboot's FSP bindings to become compatible. Cannonlake, Whiskeylake require an FSP release. Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28593 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/fsp')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h48
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h850
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h1589
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h67
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h48
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h2839
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h3318
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h136
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h270
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h71
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h48
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h1692
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h2991
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h271
14 files changed, 0 insertions, 14238 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h
deleted file mode 100644
index 5f4cb66dd0..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspUpd.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/** @file
-
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPUPD_H__
-#define __FSPUPD_H__
-
-#include <FspEas.h>
-
-#pragma pack(1)
-
-#define FSPT_UPD_SIGNATURE 0x545F4450554C5041 /* 'APLUPD_T' */
-
-#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'APLUPD_M' */
-
-#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'APLUPD_S' */
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h
deleted file mode 100644
index 3cfbd71620..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h
+++ /dev/null
@@ -1,850 +0,0 @@
-/** @file
-
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-#define MAX_CHANNELS_NUM 4
-#define MAX_DIMMS_NUM 1
-
-typedef struct {
- UINT8 DimmId;
- UINT32 SizeInMb;
- UINT16 MfgId;
- /** Module part number for DRR3 is 18 bytes
- but DRR4 is 20 bytes as per JEDEC Spec, so
- reserving 20 bytes **/
- UINT8 ModulePartNum[20];
-} DIMM_INFO;
-
-typedef struct {
- UINT8 ChannelId;
- UINT8 DimmCount;
- DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
-} CHANNEL_INFO;
-
-typedef struct {
- UINT8 Revision;
- UINT8 DataWidth;
- /** As defined in SMBIOS 3.0 spec
- Section 7.18.2 and Table 75
- **/
- UINT16 MemoryType;
- UINT16 MemoryFrequencyInMHz;
- /** As defined in SMBIOS 3.0 spec
- Section 7.17.3 and Table 72
- **/
- UINT8 ErrorCorrectionType;
- UINT8 ChannelCount;
- CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
-} FSP_SMBIOS_MEMORY_INFO;
-
-
-/** Fsp M Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Debug Serial Port Base address
- Debug serial port base address. This option will be used only when the 'Serial Port
- Debug Device' option is set to 'External Device'. 0x00000000(Default).
-**/
- UINT32 SerialDebugPortAddress;
-
-/** Offset 0x0044 - Debug Serial Port Type
- 16550 compatible debug serial port resource type. NONE means no serial port support.
- 0x02:MMIO(Default).
- 0:NONE, 1:I/O, 2:MMIO
-**/
- UINT8 SerialDebugPortType;
-
-/** Offset 0x0045 - Serial Port Debug Device
- Select active serial port device for debug. For SOC UART devices,'Debug Serial Port
- Base' options will be ignored. 0x02:SOC UART2(Default).
- 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device
-**/
- UINT8 SerialDebugPortDevice;
-
-/** Offset 0x0046 - Debug Serial Port Stride Size
- Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).
- 0:1, 2:4
-**/
- UINT8 SerialDebugPortStrideSize;
-
-/** Offset 0x0047 - Memory Fast Boot
- Enable/Disable MRC fast boot support. 0x00:Disable, 0x01:Enable(Default).
- $EN_DIS
-**/
- UINT8 MrcFastBoot;
-
-/** Offset 0x0048 - Integrated Graphics Device
- Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video
- Adaptor. Disable: Always disable IGD. 0x00:Disable, 0x01:Enable(Default).
- $EN_DIS
-**/
- UINT8 Igd;
-
-/** Offset 0x0049 - DVMT Pre-Allocated
- Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal
- Graphics Device. 0x02:64 MB(Default).
- 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256
- MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB,
- 0x0F:480 MB, 0x10:512 MB
-**/
- UINT8 IgdDvmt50PreAlloc;
-
-/** Offset 0x004A - Aperture Size
- Select the Aperture Size used by the Internal Graphics Device. 0x1:128 MB(Default),
- 0x2:256 MB, 0x3:512 MB.
- 0x1:128 MB, 0x2:256 MB, 0x3:512 MB
-**/
- UINT8 IgdApertureSize;
-
-/** Offset 0x004B - GTT Size
- Select the GTT Size used by the Internal Graphics Device. 0x1:2 MB, 0x2:4 MB, 0x3:8
- MB(Default).
- 0x1:2 MB, 0x2:4 MB, 0x3:8 MB
-**/
- UINT8 GttSize;
-
-/** Offset 0x004C - Primary Display
- Select which of IGD/PCI Graphics device should be Primary Display. 0x0:AUTO(Default),
- 0x2:IGD, 0x3:PCI
- 0x0:AUTO, 0x2:IGD, 0x3:PCI
-**/
- UINT8 PrimaryVideoAdaptor;
-
-/** Offset 0x004D - Package
- NOTE: Specifies CA Mapping for all technologies. Supported CA Mappings: 0 - SODIMM(Default);
- 1 - BGA; 2 - BGA mirrored (LPDDR3 only); 3 - SODIMM/UDIMM with Rank 1 Mirrored
- (DDR3L); Refer to the IAFW spec for specific details about each CA mapping.
- 0x0:SODIMM, 0x1:BGA, 0x2:BGA mirrored (LPDDR3 only), 0x3:SODIMM/UDIMM with Rank
- 1 Mirrored (DDR3L)
-**/
- UINT8 Package;
-
-/** Offset 0x004E - Profile
- Profile list. 0x19(Default).
- 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12,
- 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10,
- 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24,
- 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7,
- 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9,
- 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10,
- 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12,
- 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13,
- 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11,
- 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14,
- 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15,
- 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18
-**/
- UINT8 Profile;
-
-/** Offset 0x004F - MemoryDown
- Memory Down. 0x0(Default).
- 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4
-**/
- UINT8 MemoryDown;
-
-/** Offset 0x0050 - DDR3LPageSize
- NOTE: Only for memory down (soldered down memory with no SPD). 0x01:1KB(Default), 0x02:2KB.
- 0x1:1KB, 0x2:2KB
-**/
- UINT8 DDR3LPageSize;
-
-/** Offset 0x0051 - DDR3LASR
- NOTE: Only for memory down. This is specific to ddr3l and used for refresh adjustment
- in Self Refresh, does not affect LP4. 0x00:Not Supported(Default), 0x01:Supported.
- 0x0:Not Supported, 0x1:Supported
-**/
- UINT8 DDR3LASR;
-
-/** Offset 0x0052 - ScramblerSupport
- Scrambler Support - Enable or disable the memory scrambler. Data scrambling is
- provided as a means to increase signal integrity/reduce RFI generated by the DRAM
- interface. This is achieved by randomizing seed that encodes/decodes memory data
- so repeating a worse case pattern is hard to repeat. 00: Disable Scrambler Support,
- 01: Enable Scrambler Support
- $EN_DIS
-**/
- UINT8 ScramblerSupport;
-
-/** Offset 0x0053 - InterleavedMode
- This field is ignored if one of the PnP channel configurations is used. If the memory
- configuration is different, then the field is used directly to populate. 0x00:Disable(Default),
- 0x02:Enable.
- 0x0:Disable, 0x2:Enable
-**/
- UINT8 InterleavedMode;
-
-/** Offset 0x0054 - ChannelHashMask
- ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be
- modified. These inputs are not used for configurations where an optimized ChannelHashMask
- has been provided by the PnP validation teams. 0x00(Default).
-**/
- UINT16 ChannelHashMask;
-
-/** Offset 0x0056 - SliceHashMask
- ChannelHashMask and SliceHashMask allow for the channel hashing algorithm to be
- modified. These inputs are not used for configurations where an optimized ChannelHashMask
- has been provided by the PnP validation teams. 0x00(Default).
-**/
- UINT16 SliceHashMask;
-
-/** Offset 0x0058 - ChannelsSlicesEnable
- ChannelSlicesEnable field is not used at all on BXTP. The Channel Slice Configuration
- is calculated internally based on the enabled channel configuration. 0x00:Disable(Default),
- 0x01:Enable.
- $EN_DIS
-**/
- UINT8 ChannelsSlicesEnable;
-
-/** Offset 0x0059 - MinRefRate2xEnable
- Provided as a means to defend against Row-Hammer attacks. 0x00:Disable(Default),
- 0x01:Enable.
- $EN_DIS
-**/
- UINT8 MinRefRate2xEnable;
-
-/** Offset 0x005A - DualRankSupportEnable
- Dual Rank Support Enable. 0x00:Disable, 0x01:Enable(Default).
- $EN_DIS
-**/
- UINT8 DualRankSupportEnable;
-
-/** Offset 0x005B - RmtMode
- Rank Margin Tool Mode. 0x00(Default), 0x3(Enabled).
- 0x0:Disabled, 0x3:Enabled
-**/
- UINT8 RmtMode;
-
-/** Offset 0x005C - MemorySizeLimit
- Memory Size Limit: This value is used to restrict the total amount of memory and
- the calculations based on it. Value is in MB. Example encodings are: 0x400 = 1GB,
- 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default)
-**/
- UINT16 MemorySizeLimit;
-
-/** Offset 0x005E - LowMemoryMaxValue
- Low Memory Max Value: This value is used to restrict the amount of memory below
- 4GB and the calculations based on it. Value is in MB.Example encodings are: 0x400
- = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. 0x0000(Default).
-**/
- UINT16 LowMemoryMaxValue;
-
-/** Offset 0x0060 - HighMemoryMaxValue
- High Memory Max Value: This value is used to restrict the amount of memory above
- 4GB and the calculations based on it. Value is in MB. Example encodings are: 0x0400:1GB,
- 0x0800:2GB, 0x1000:4GB, 0x2000:8GB. 0x00(Default).
-**/
- UINT16 HighMemoryMaxValue;
-
-/** Offset 0x0062 - DisableFastBoot
- 00:Disabled; Use saved training data (if valid) after first boot(Default), 01:Enabled;
- Full re-train of memory on every boot.
- $EN_DIS
-**/
- UINT8 DisableFastBoot;
-
-/** Offset 0x0063 - DIMM0SPDAddress
- DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA0(Default).
-**/
- UINT8 DIMM0SPDAddress;
-
-/** Offset 0x0064 - DIMM1SPDAddress
- DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. 0xA4(Default).
-**/
- UINT8 DIMM1SPDAddress;
-
-/** Offset 0x0065 - Ch0_RankEnable
- NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
- NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
- 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
- set to 1 to enable use of this rank.
-**/
- UINT8 Ch0_RankEnable;
-
-/** Offset 0x0066 - Ch0_DeviceWidth
- NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
- (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
- and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
- device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
- 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
-**/
- UINT8 Ch0_DeviceWidth;
-
-/** Offset 0x0067 - Ch0_DramDensity
- NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
- density per rank (per Chip Select). The simplest way of identifying the density
- per rank is to divide the total SoC memory channel density by the number of ranks.
- For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
- 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
- a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
- 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
- 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
-**/
- UINT8 Ch0_DramDensity;
-
-/** Offset 0x0068 - Ch0_Option
- BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
- 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
- Bank Address Hashing Enable. See Address Mapping section for full description:
- 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
- CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
- designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
- CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
- specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
-**/
- UINT8 Ch0_Option;
-
-/** Offset 0x0069 - Ch0_OdtConfig
- [0] RX ODT - DDR3L & LPDDR3 only: Change the READ ODT strength , for SOC termination
- during a READ transaction, ON DQ BITs. STRONG ==> 60 OHMS roughly, WEAK ==> 120
- OHMS or so roughly. Purpose: Save power on these technologies which burn power
- directly proportional to ODT strength, because ODT looks like a PU and PD (e.g.
- a resistor divider, which always burns power when ODT is ON). 0 - WEAK_ODT_CONFIG,
- 1 - STRONG_ODT_CONFIG. LPDDR4: X - Don't Care. [1] CA ODT - LPDDR4 Only: The
- customer needs to choose this based on their actual board strapping (how they tie
- the DRAM's ODT PINs). Effect: LPDDR4 MR11 will be set based on this setting. CAODT_A_B_HIGH_LOW
- ==> MR11 = 0x34, which is CA ODT = 80 ohms. CAODT_A_B_HIGH_HIGH ==> MR11 = 0x24,
- which is CA ODT = 120 ohms (results in 60 ohm final effective impedance on CA/CLK/CS
- signals). Purpose: To improve signal integrity and provide a much more optimized
- CA VREF value during training. Not to save power. 0 - ODT_AB_HIGH_LOW (default),
- 1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:
- 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120
- Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care
-**/
- UINT8 Ch0_OdtConfig;
-
-/** Offset 0x006A - Ch0_TristateClk1
- Not used
-**/
- UINT8 Ch0_TristateClk1;
-
-/** Offset 0x006B - Ch0_Mode2N
- DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
- mode that provides more setup and hold time for DRAM commands on the DRAM command
- bus. This is useful for platforms with unusual CMD bus routing or marginal signal
- integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
- Control training), 1 - Force 2N Mode
- 0x0:Auto, 0x1:Force 2N CMD Timing Mode
-**/
- UINT8 Ch0_Mode2N;
-
-/** Offset 0x006C - Ch0_OdtLevels
- Parameter used to determine if ODT will be held high or low: 0 - ODT Connected to
- SoC, 1 - ODT held high
-**/
- UINT8 Ch0_OdtLevels;
-
-/** Offset 0x006D - Ch1_RankEnable
- NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
- NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
- 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
- set to 1 to enable use of this rank.
-**/
- UINT8 Ch1_RankEnable;
-
-/** Offset 0x006E - Ch1_DeviceWidth
- NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
- (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
- and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
- device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
- 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
-**/
- UINT8 Ch1_DeviceWidth;
-
-/** Offset 0x006F - Ch1_DramDensity
- NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
- density per rank (per Chip Select). The simplest way of identifying the density
- per rank is to divide the total SoC memory channel density by the number of ranks.
- For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
- 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
- a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
- 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
- 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
-**/
- UINT8 Ch1_DramDensity;
-
-/** Offset 0x0070 - Ch1_Option
- BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
- 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
- Bank Address Hashing Enable. See Address Mapping section for full description:
- 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
- CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
- designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
- CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
- specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
-**/
- UINT8 Ch1_Option;
-
-/** Offset 0x0071 - Ch1_OdtConfig
- BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;
- LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,
- 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:
- X = Don't Care
-**/
- UINT8 Ch1_OdtConfig;
-
-/** Offset 0x0072 - Ch1_TristateClk1
- Not used
-**/
- UINT8 Ch1_TristateClk1;
-
-/** Offset 0x0073 - Ch1_Mode2N
- DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
- mode that provides more setup and hold time for DRAM commands on the DRAM command
- bus. This is useful for platforms with unusual CMD bus routing or marginal signal
- integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
- Control training), 1 - Force 2N Mode
- 0x0:Auto, 0x1:Force 2N CMD Timing Mode
-**/
- UINT8 Ch1_Mode2N;
-
-/** Offset 0x0074 - Ch1_OdtLevels
- DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
- (default), 1 - ODT_AB_HIGH_HIGH
-**/
- UINT8 Ch1_OdtLevels;
-
-/** Offset 0x0075 - Ch2_RankEnable
- NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
- NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
- 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
- set to 1 to enable use of this rank.
-**/
- UINT8 Ch2_RankEnable;
-
-/** Offset 0x0076 - Ch2_DeviceWidth
- NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
- (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
- and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
- device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
- 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
-**/
- UINT8 Ch2_DeviceWidth;
-
-/** Offset 0x0077 - Ch2_DramDensity
- NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
- density per rank (per Chip Select). The simplest way of identifying the density
- per rank is to divide the total SoC memory channel density by the number of ranks.
- For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
- 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
- a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
- 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
- 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
-**/
- UINT8 Ch2_DramDensity;
-
-/** Offset 0x0078 - Ch2_Option
- BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
- 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
- Bank Address Hashing Enable. See Address Mapping section for full description:
- 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
- CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
- designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
- CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
- specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
-**/
- UINT8 Ch2_Option;
-
-/** Offset 0x0079 - Ch2_OdtConfig
- BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;
- LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,
- 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:
- X = Don't Care
-**/
- UINT8 Ch2_OdtConfig;
-
-/** Offset 0x007A - Ch2_TristateClk1
- Not used
-**/
- UINT8 Ch2_TristateClk1;
-
-/** Offset 0x007B - Ch2_Mode2N
- DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
- mode that provides more setup and hold time for DRAM commands on the DRAM command
- bus. This is useful for platforms with unusual CMD bus routing or marginal signal
- integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
- Control training), 1 - Force 2N Mode
- 0x0:Auto, 0x1:Force 2N CMD Timing Mode
-**/
- UINT8 Ch2_Mode2N;
-
-/** Offset 0x007C - Ch2_OdtLevels
- DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
- (default), 1 - ODT_AB_HIGH_HIGH
-**/
- UINT8 Ch2_OdtLevels;
-
-/** Offset 0x007D - Ch3_RankEnable
- NOTE: Only for memory down. This is a bit mask which specifies what ranks are enabled.
- NOTE: Only for memory down (soldered down memory with no SPD): BIT[0] Enable Rank
- 0: Must be set to 1 to enable use of this rank; BIT1[1] Enable Rank 1: Must be
- set to 1 to enable use of this rank.
-**/
- UINT8 Ch3_RankEnable;
-
-/** Offset 0x007E - Ch3_DeviceWidth
- NOTE: Only for memory down. Must specify the DRAM device width per DRAM channel
- (not to be confused with the SoC Memory Channel width which is always x32 for LPDDR3\LPDDR4
- and x64 for DDR3L). LPDDR4 devices typically have two channels per die and a x16
- device width: 00 - x8; 01 - x16; 10 - x32; 11 - x64
- 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64
-**/
- UINT8 Ch3_DeviceWidth;
-
-/** Offset 0x007F - Ch3_DramDensity
- NOTE: Only for memory down. For LPDDR3 and LPDDR4: Must specify the DRAM device
- density per rank (per Chip Select). The simplest way of identifying the density
- per rank is to divide the total SoC memory channel density by the number of ranks.
- For DDR3L: Must specify the DRAM device density per DRAM device. For example, an
- 8GB 2Rx8 configuration will utilize sixteen 4Gb density DRAMS. In this configuration,
- a 4Gb density setting would be selected in the MRC: 000 - 4Gb; 001 - 6Gb; 010 -
- 8Gb; 011 - 12Gb; 100 - 16Gb; 101 - 2Gb; 110-111 - Reserved
- 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb
-**/
- UINT8 Ch3_DramDensity;
-
-/** Offset 0x0080 - Ch3_Option
- BIT[0] Rank Select Interleaving Enable. See Address Mapping section for full description:
- 0 - Rank Select Interleaving disabled; 1 - Rank Select Interleaving enabled. BIT[1]
- Bank Address Hashing Enable. See Address Mapping section for full description:
- 0 - Bank Address Hashing disabled; 1 - Bank Address Hashing enabled. BIT[2] CH1
- CLK Disable. Disables the CH1 CLK PHY Signal when set to 1. This is used on board
- designs where the CH1 CLK is not routed and left floating or stubbed out: 0 - CH1
- CLK is enabled; 1 - CH1 CLK is disabled. BIT[3] Reserved; BIT[5:4] This register
- specifies the address mapping to be used: 00 - 1KB (A); 01 - 2KB (B)
-**/
- UINT8 Ch3_Option;
-
-/** Offset 0x0081 - Ch3_OdtConfig
- BIT[0] TX ODT: DDR3L & LPDDR3 only: 0 - WEAK_ODT_CONFIG, 1 - STRONG_ODT_CONFIG;
- LPDDR4: X = Don't Care; BIT[4] RX ODT DDR3L only: 0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_60_OHMS,
- 1 = RZQ/2 (120 Ohms) = MRC_SMIP_DDR3L_RX_ODT_RTT_WR_120_OHMS; LPDDR3 & LPDDR4:
- X = Don't Care
-**/
- UINT8 Ch3_OdtConfig;
-
-/** Offset 0x0082 - Ch3_TristateClk1
- Not used
-**/
- UINT8 Ch3_TristateClk1;
-
-/** Offset 0x0083 - Ch3_Mode2N
- DDR3L Only: Configures the DDR3L command timing mode. 2N Mode is a stretched command
- mode that provides more setup and hold time for DRAM commands on the DRAM command
- bus. This is useful for platforms with unusual CMD bus routing or marginal signal
- integrity: 0 - Auto (1N or 2N mode is automatically selected during Command and
- Control training), 1 - Force 2N Mode
- 0x0:Auto, 0x1:Force 2N CMD Timing Mode
-**/
- UINT8 Ch3_Mode2N;
-
-/** Offset 0x0084 - Ch3_OdtLevels
- DDR3L Only: Parameter used to determine if ODT will be held high or low: 0 - ODT_AB_HIGH_LOW
- (default), 1 - ODT_AB_HIGH_HIGH
-**/
- UINT8 Ch3_OdtLevels;
-
-/** Offset 0x0085 - RmtCheckRun
- Parameter used to determine whether to run the margin check. Bit 0 is used for MINIMUM
- MARGIN CHECK and bit 1 is used for DEGRADE MARGIN CHECK
-**/
- UINT8 RmtCheckRun;
-
-/** Offset 0x0086 - RmtMarginCheckScaleHighThreshold
- Percentage used to determine the margin tolerances over the failing margin.
-**/
- UINT16 RmtMarginCheckScaleHighThreshold;
-
-/** Offset 0x0088 - Ch0_Bit_swizzling
- Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. Frequently
- asked questions: Q: The DQS (strobes) need to go with the corresponding byte lanes
- on the DDR module. Are the DQS being swapped around as well? Ans: Yes, DQ strobes
- need to follow the DQ byte lane they correspond too. So for example if you have
- DQ[7:0] swapped with DQ[15:8], DQS0 pair also need to be swapped with DQS1 pair.
- Also, the spreadsheet used for Amenia is essentially a swizzle value lookup that
- specifies what DRAM DQ bit a particular SoC DQ bit is connected to. Some confusion
- can arrise from the fact that the indexes to the array do not necessarily map 1:1
- to an SoC DQ pin. For example, the CH0 array at index 0 maps to SoC DQB8. The value
- of 9 at index 0 tells us that SoC DQB8 is connected to DRAM DQA9. Q: The PDG indicates
- a 2 physical channels need to be stuffed and operated together. Are the CHx_A and
- CHx_B physical channels operated in tandem or completely separate? If separate,
- why requirement of pairing them? Ans: We have 2 PHY instances on the SoC each supporting
- up to 2 x32 LP4 channels. If you have 4 channels both PHYs are active, but if you
- have 2 channels in order to power gate one PHY, those two channel populated must
- be on one PHY instance. So yes all channels are independent of each other, but
- there are some restrictions on how they need to be populated. Q: How is it that
- an LPDDR4 device is identified as having a x16 width when all 32-bits are used
- at the same time with a single chip select? That's effectively a x32 device. Ans:LPDDR4
- DRAM devices are x16. Each die has 2 x16 devices on them. To make a x32 channel
- the CS of the two devices in the same die are connected together to make a single
- rank of one x32 channel (SDP). The second die in the DDP package makes the second rank.
-**/
- UINT8 Ch0_Bit_swizzling[32];
-
-/** Offset 0x00A8 - Ch1_Bit_swizzling
- Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
-**/
- UINT8 Ch1_Bit_swizzling[32];
-
-/** Offset 0x00C8 - Ch2_Bit_swizzling
- Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
-**/
- UINT8 Ch2_Bit_swizzling[32];
-
-/** Offset 0x00E8 - Ch3_Bit_swizzling
- Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32.
-**/
- UINT8 Ch3_Bit_swizzling[32];
-
-/** Offset 0x0108 - MsgLevelMask
- 32 bits used to mask out debug messages. Masking out bit 0 mask all other messages.
-**/
- UINT32 MsgLevelMask;
-
-/** Offset 0x010C
-**/
- UINT8 UnusedUpdSpace0[4];
-
-/** Offset 0x0110 - PreMem GPIO Pin Number for each table
- Number of Pins in each PreMem GPIO Table. 0(Default).
-**/
- UINT8 PreMemGpioTablePinNum[4];
-
-/** Offset 0x0114 - PreMem GPIO Table Pointer
- Pointer to Array of pointers to PreMem GPIO Table. 0x00000000(Default).
-**/
- UINT32 PreMemGpioTablePtr;
-
-/** Offset 0x0118 - PreMem GPIO Table Entry Number. Currently maximum entry number is 4
- Number of Entries in PreMem GPIO Table. 0(Default).
-**/
- UINT8 PreMemGpioTableEntryNum;
-
-/** Offset 0x0119 - Enhance the port 8xh decoding
- Enable/Disable Enhance the port 8xh decoding. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 EnhancePort8xhDecoding;
-
-/** Offset 0x011A - SPD Data Write
- Enable/Disable SPD data write on the SMBUS. 0x00:Disable(Default), 0x01:Enable.
- $EN_DIS
-**/
- UINT8 SpdWriteEnable;
-
-/** Offset 0x011B - MRC Training Data Saving
- Enable/Disable MRC training data saving in FSP. 0x00:Disable(Default), 0x01:Enable.
- $EN_DIS
-**/
- UINT8 MrcDataSaving;
-
-/** Offset 0x011C - OEM File Loading Address
- Determine the memory base address to load a specified file from CSE file system
- after memory is available.
-**/
- UINT32 OemLoadingBase;
-
-/** Offset 0x0120 - OEM File Name to Load
- Specify a file name to load from CSE file system after memory is available. Empty
- indicates no file needs to be loaded.
-**/
- UINT8 OemFileName[16];
-
-/** Offset 0x0130
-**/
- VOID* MrcBootDataPtr;
-
-/** Offset 0x0134 - eMMC Trace Length
- Select eMMC trace length to load OEM file from when loading OEM file name is specified.
- 0x0:Long(Default), 0x1:Short.
- 0x0:Long, 0x1:Short
-**/
- UINT8 eMMCTraceLen;
-
-/** Offset 0x0135 - Skip CSE RBP to support zero sized IBB
- Enable/Disable skip CSE RBP for bootloader which loads IBB without assistance of
- CSE. 0x00:Disable(Default), 0x01:Enable.
- $EN_DIS
-**/
- UINT8 SkipCseRbp;
-
-/** Offset 0x0136 - Npk Enable
- Enable/Disable Npk. 0:Disable, 1:Enable, 2:Debugger, 3:Auto(Default).
- 0:Disable, 1:Enable, 2:Debugger, 3:Auto
-**/
- UINT8 NpkEn;
-
-/** Offset 0x0137 - FW Trace Enable
- Enable/Disable FW Trace. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 FwTraceEn;
-
-/** Offset 0x0138 - FW Trace Destination
- FW Trace Destination. 1-NPK_TRACE_TO_MEMORY, 2-NPK_TRACE_TO_DCI, 3-NPK_TRACE_TO_BSSB,
- 4-NPK_TRACE_TO_PTI(Default).
-**/
- UINT8 FwTraceDestination;
-
-/** Offset 0x0139 - NPK Recovery Dump
- Enable/Disable NPK Recovery Dump. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 RecoverDump;
-
-/** Offset 0x013A - Memory Region 0 Buffer WrapAround
- Memory Region 0 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
-**/
- UINT8 Msc0Wrap;
-
-/** Offset 0x013B - Memory Region 1 Buffer WrapAround
- Memory Region 1 Buffer WrapAround. 0-n0-warp, 1-warp(Default).
-**/
- UINT8 Msc1Wrap;
-
-/** Offset 0x013C - Memory Region 0 Buffer Size
- Memory Region 0 Buffer Size. 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
- 6-512MB, 7-1GB.
-**/
- UINT32 Msc0Size;
-
-/** Offset 0x0140 - Memory Region 1 Buffer Size
- Memory Region 1 Buffer Size, 0-0MB(Default), 1-1MB, 2-8MB, 3-64MB, 4-128MB, 5-256MB,
- 6-512MB, 7-1GB.
-**/
- UINT32 Msc1Size;
-
-/** Offset 0x0144 - PTI Mode
- PTI Mode. 0-0ff, 1-x4(Default), 2-x8, 3-x12, 4-x16.
-**/
- UINT8 PtiMode;
-
-/** Offset 0x0145 - PTI Training
- PTI Training. 0-off(Default), 1-6=1-6.
-**/
- UINT8 PtiTraining;
-
-/** Offset 0x0146 - PTI Speed
- PTI Speed. 0-full, 1-half, 2-quarter(Default).
-**/
- UINT8 PtiSpeed;
-
-/** Offset 0x0147 - Punit Message Level
- Punit Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
-**/
- UINT8 PunitMlvl;
-
-/** Offset 0x0148 - PMC Message Level
- PMC Message Output Verbosity Level. 0, 1(Default), 2-4=2-4.
-**/
- UINT8 PmcMlvl;
-
-/** Offset 0x0149 - SW Trace Enable
- Enable/Disable SW Trace. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 SwTraceEn;
-
-/** Offset 0x014A - Periodic Retraining Disable
- Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic
- Retraining for debug purposes. Periodic Retraining should be enabled in production.
- Periodic retraining allows the platform to operate reliably over a larger voltage
- and temperature range. This field has no effect for DDR3L and LPDDR3 memory type
- configurations. 0x00: Enable Periodic Retraining (default); 0x01: Disable Periodic
- Retraining (debug configuration only)
- 0x0:Enabled, 0x1:Disabled
-**/
- UINT8 PeriodicRetrainingDisable;
-
-/** Offset 0x014B - Enable Reset System
- Enable FSP to trigger reset instead of returning reset request. 0x00: Return the
- Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside
- FSP instead of returning from the API.
- 0x0:Disabled, 0x1:Eabled
-**/
- UINT8 EnableResetSystem;
-
-/** Offset 0x014C - Enable HECI2 in S3 resume path
- Enable HECI2 in S3 resume path. 0x00: Skip HECI2 initialization in S3 resume. ;
- 0x01: Enable HECI2 in S3 resume path.(Default)
- 0x0:Disabled, 0x1:Eabled
-**/
- UINT8 EnableS3Heci2;
-
-/** Offset 0x014D
-**/
- UINT8 UnusedUpdSpace1[3];
-
-/** Offset 0x0150
-**/
- VOID* VariableNvsBufferPtr;
-
-/** Offset 0x0154
-**/
- UINT8 ReservedFspmUpd[12];
-} FSP_M_CONFIG;
-
-/** Fsp M UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPM_ARCH_UPD FspmArchUpd;
-
-/** Offset 0x0040
-**/
- FSP_M_CONFIG FspmConfig;
-
-/** Offset 0x0160
-**/
- UINT8 UnusedUpdSpace2[158];
-
-/** Offset 0x01FE
-**/
- UINT16 UpdTerminator;
-} FSPM_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h
deleted file mode 100644
index 82a224d629..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h
+++ /dev/null
@@ -1,1589 +0,0 @@
-/** @file
-
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-/** Fsp S Configuration
-**/
-typedef struct {
-
-/** Offset 0x0020 - ActiveProcessorCores
- Number of active cores. 0:Disable(Default), 1:Enable.
-**/
- UINT8 ActiveProcessorCores;
-
-/** Offset 0x0021 - Disable Core1
- Disable/Enable Core1. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 DisableCore1;
-
-/** Offset 0x0022 - Disable Core2
- Disable/Enable Core2. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 DisableCore2;
-
-/** Offset 0x0023 - Disable Core3
- Disable/Enable Core3. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 DisableCore3;
-
-/** Offset 0x0024 - VMX Enable
- Enable or Disable VMX. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 VmxEnable;
-
-/** Offset 0x0025 - Memory region allocation for Processor Trace
- Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to
- 128MB (0xF); <b>0xFF: Disable. 0xFF:Disable(Default)
-**/
- UINT8 ProcTraceMemSize;
-
-/** Offset 0x0026 - Enable Processor Trace
- Enable or Disable Processor Trace feature. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 ProcTraceEnable;
-
-/** Offset 0x0027 - Eist
- Enable or Disable Intel SpeedStep Technology. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 Eist;
-
-/** Offset 0x0028 - Boot PState
- Boot PState with HFM or LFM. 0:HFM(Default), 1:LFM.
-**/
- UINT8 BootPState;
-
-/** Offset 0x0029 - CPU power states (C-states)
- Enable or Disable CPU power states (C-states). 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 EnableCx;
-
-/** Offset 0x002A - Enhanced C-states
- Enable or Disable Enhanced C-states. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 C1e;
-
-/** Offset 0x002B - Bi-Directional PROCHOT#
- Enable or Disable Bi-Directional PROCHOT#. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 BiProcHot;
-
-/** Offset 0x002C - Max Pkg Cstate
- Max Pkg Cstate. 0:PkgC0C1, 1:PkgC2, 2:PkgC3(Default), 3:PkgC6, 4:PkgC7, 5:PkgC7s,
- 6:PkgC8, 7:PkgC9, 8:PkgC10, 9:PkgCMax, 254:PkgCpuDefault, 255:PkgAuto.
-**/
- UINT8 PkgCStateLimit;
-
-/** Offset 0x002D - C-State auto-demotion
- C-State Auto Demotion. 0:Disable(Default) C1 and C3 Auto-demotion, 1:Enable C3/C6/C7
- Auto-demotion to C1, 2:Enable C6/C7 Auto-demotion to C3, 3:Enable C6/C7 Auto-demotion
- to C1 and C3.
-**/
- UINT8 CStateAutoDemotion;
-
-/** Offset 0x002E - C-State un-demotion
- C-State un-demotion. 0:Disable(Default) C1 and C3 Un-demotion, 1:Enable C1 Un-demotion,
- 2:Enable C3 Un-demotion, 3:Enable C1 and C3 Un-demotion.
-**/
- UINT8 CStateUnDemotion;
-
-/** Offset 0x002F - Max Core C-State
- Max Core C-State. 0:Unlimited, 1:C1, 2:C3, 3:C6, 4:C7, 5:C8, 6:C9, 7:C10, 8:CCx(Default).
-**/
- UINT8 MaxCoreCState;
-
-/** Offset 0x0030 - Package C-State Demotion
- Enable or Disable Package Cstate Demotion. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 PkgCStateDemotion;
-
-/** Offset 0x0031 - Package C-State Un-demotion
- Enable or Disable Package Cstate UnDemotion. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 PkgCStateUnDemotion;
-
-/** Offset 0x0032 - Turbo Mode
- Enable or Disable long duration Turbo Mode. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 TurboMode;
-
-/** Offset 0x0033 - SC HDA Verb Table Entry Number
- Number of Entries in Verb Table. 0(Default).
-**/
- UINT8 HdaVerbTableEntryNum;
-
-/** Offset 0x0034 - SC HDA Verb Table Pointer
- Pointer to Array of pointers to Verb Table. 0x00000000(Default).
-**/
- UINT32 HdaVerbTablePtr;
-
-/** Offset 0x0038 - Enable/Disable P2SB device hidden.
- Enable/Disable P2SB device hidden. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 P2sbUnhide;
-
-/** Offset 0x0039 - IPU Enable/Disable
- Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 IpuEn;
-
-/** Offset 0x003A - IMGU ACPI mode selection
- 0:Auto, 1:IGFX Child device(Default), 2:ACPI device.
- 0:Disable, 1:IGFX Child device, 2:ACPI device
-**/
- UINT8 IpuAcpiMode;
-
-/** Offset 0x003B - Enable ForceWake
- Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 ForceWake;
-
-/** Offset 0x003C - GttMmAdr
- GttMmAdr structure for initialization. 0xBF000000(Default).
-**/
- UINT32 GttMmAdr;
-
-/** Offset 0x0040 - GmAdr
- GmAdr structure for initialization. 0xA0000000(Default).
-**/
- UINT32 GmAdr;
-
-/** Offset 0x0044 - Enable PavpLock
- Enable/disable PavpLock. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 PavpLock;
-
-/** Offset 0x0045 - Enable GraphicsFreqModify
- Enable/disable GraphicsFreqModify. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 GraphicsFreqModify;
-
-/** Offset 0x0046 - Enable GraphicsFreqReq
- Enable/disable GraphicsFreqReq. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 GraphicsFreqReq;
-
-/** Offset 0x0047 - Enable GraphicsVideoFreq
- Enable/disable GraphicsVideoFreq. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 GraphicsVideoFreq;
-
-/** Offset 0x0048 - Enable PmLock
- Enable/disable PmLock. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 PmLock;
-
-/** Offset 0x0049 - Enable DopClockGating
- Enable/disable DopClockGating. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 DopClockGating;
-
-/** Offset 0x004A - Enable UnsolicitedAttackOverride
- Enable/disable UnsolicitedAttackOverride. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 UnsolicitedAttackOverride;
-
-/** Offset 0x004B - Enable WOPCMSupport
- Enable/disable WOPCMSupport. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 WOPCMSupport;
-
-/** Offset 0x004C - Enable WOPCMSize
- Enable/disable WOPCMSize. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 WOPCMSize;
-
-/** Offset 0x004D - Enable PowerGating
- Enable/disable PowerGating. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 PowerGating;
-
-/** Offset 0x004E - Enable UnitLevelClockGating
- Enable/disable UnitLevelClockGating. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 UnitLevelClockGating;
-
-/** Offset 0x004F - Enable FastBoot
- Enable/disable FastBoot. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 FastBoot;
-
-/** Offset 0x0050 - Enable DynSR
- Enable/disable DynSR. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 DynSR;
-
-/** Offset 0x0051 - Enable SaIpuEnable
- Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 SaIpuEnable;
-
-/** Offset 0x0052 - GT PM Support
- Enable/Disable GT power management support. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 PmSupport;
-
-/** Offset 0x0053 - RC6(Render Standby)
- Enable/Disable render standby support. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 EnableRenderStandby;
-
-/** Offset 0x0054 - BMP Logo Data Size
- BMP logo data buffer size. 0x00000000(Default).
-**/
- UINT32 LogoSize;
-
-/** Offset 0x0058 - BMP Logo Data Pointer
- BMP logo data pointer to a BMP format buffer. 0x00000000(Default).
-**/
- UINT32 LogoPtr;
-
-/** Offset 0x005C - Graphics Configuration Data Pointer
- Graphics configuration data used for initialization. 0x00000000(Default).
-**/
- UINT32 GraphicsConfigPtr;
-
-/** Offset 0x0060 - PAVP Enable
- Enable/Disable Protected Audio Visual Path (PAVP). 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 PavpEnable;
-
-/** Offset 0x0061 - PAVP PR3
- Enable/Disable PAVP PR3 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 PavpPr3;
-
-/** Offset 0x0062 - CdClock Frequency selection
- 0:144MHz, 1:288MHz, 2:384MHz, 3:576MHz, 4:624MHz(Default).
- 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz
-**/
- UINT8 CdClock;
-
-/** Offset 0x0063 - Enable/Disable PeiGraphicsPeimInit
- Enable/Disable PeiGraphicsPeimInit 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 PeiGraphicsPeimInit;
-
-/** Offset 0x0064 - Write Protection Support
- Enable/disable Write Protection. 0:Disable, 1:Enable(Default).
-**/
- UINT8 WriteProtectionEnable[5];
-
-/** Offset 0x0069 - Read Protection Support
- Enable/disable Read Protection. 0:Disable, 1:Enable(Default).
-**/
- UINT8 ReadProtectionEnable[5];
-
-/** Offset 0x006E - Protected Range Limitation
- The address of the upper limit of protection, 0x0FFFh(Default).
-**/
- UINT16 ProtectedRangeLimit[5];
-
-/** Offset 0x0078 - Protected Range Base
- The base address of the upper limit of protection. 0x0000(Default).
-**/
- UINT16 ProtectedRangeBase[5];
-
-/** Offset 0x0082 - Enable SC Gaussian Mixture Models
- Enable/disable SC Gaussian Mixture Models. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 Gmm;
-
-/** Offset 0x0083 - GMM Clock Gating - PGCB Clock Trunk
- Enable/disable PGCB Clock Trunk. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingPgcbClkTrunk;
-
-/** Offset 0x0084 - GMM Clock Gating - Sideband
- Enable/disable Sideband. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingSb;
-
-/** Offset 0x0085 - GMM Clock Gating - Sideband
- Enable/disable Sideband. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingSbClkTrunk;
-
-/** Offset 0x0086 - GMM Clock Gating - Sideband Clock Partition
- Enable/disable Sideband Clock Partition. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingSbClkPartition;
-
-/** Offset 0x0087 - GMM Clock Gating - Core
- Enable/disable Core. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingCore;
-
-/** Offset 0x0088 - GMM Clock Gating - DMA
- Enable/disable DMA. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingDma;
-
-/** Offset 0x0089 - GMM Clock Gating - Register Access
- Enable/disable Register Access. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingRegAccess;
-
-/** Offset 0x008A - GMM Clock Gating - Host
- Enable/disable Host. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingHost;
-
-/** Offset 0x008B - GMM Clock Gating - Partition
- Enable/disable Partition. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingPartition;
-
-/** Offset 0x008C - Clock Gating - Trunk
- Enable/disable Trunk. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ClkGatingTrunk;
-
-/** Offset 0x008D - HD Audio Support
- Enable/disable HDA Audio Feature. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 HdaEnable;
-
-/** Offset 0x008E - HD Audio DSP Support
- Enable/disable HDA Audio DSP Feature. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 DspEnable;
-
-/** Offset 0x008F - Azalia wake-on-ring
- Enable/disable Azalia wake-on-ring. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 Pme;
-
-/** Offset 0x0090 - HD-Audio I/O Buffer Ownership
- Set HD-Audio I/O Buffer Ownership. 0:HD-Audio link owns all the I/O buffers(Default)
- 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and
- I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers
-**/
- UINT8 HdAudioIoBufferOwnership;
-
-/** Offset 0x0091 - HD-Audio I/O Buffer Voltage
- HD-Audio I/O Buffer Voltage Mode Selectiton . 0:3.3V(Default), 1:1.8V.
- 0: 3.3V, 1: 1.8V
-**/
- UINT8 HdAudioIoBufferVoltage;
-
-/** Offset 0x0092 - HD-Audio Virtual Channel Type
- HD-Audio Virtual Channel Type Selectiton. 0:VC0(Default), 1:VC1.
- 0: VC0, 1: VC1
-**/
- UINT8 HdAudioVcType;
-
-/** Offset 0x0093 - HD-Audio Link Frequency
- HD-Audio Virtual Channel Type Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
- 4:96MHz, 5:Invalid.
- 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
-**/
- UINT8 HdAudioLinkFrequency;
-
-/** Offset 0x0094 - HD-Audio iDisp-Link Frequency
- HD-Audio iDisp-Link Frequency Selectiton. 0:6MHz(Default), 1:12MHz, 2:24MHz, 3:48MHz,
- 4:96MHz, 5:Invalid.
- 0: 6MHz, 1: 12MHz, 2: 24MHz, 3: 48MHz, 4: 96MHz, 5: Invalid
-**/
- UINT8 HdAudioIDispLinkFrequency;
-
-/** Offset 0x0095 - HD-Audio iDisp-Link T-Mode
- HD-Audio iDisp-Link T-Mode Selectiton. 0:2T(Default), 1:1T.
- 0: 2T, 1: 1T
-**/
- UINT8 HdAudioIDispLinkTmode;
-
-/** Offset 0x0096 - HD-Audio Disp DMIC
- HD-Audio Disp DMIC Selectiton. 0:Disable, 1:2ch array(Default), 2:4ch array.
- 0: Disable, 1: 2ch array, 2: 4ch array
-**/
- UINT8 DspEndpointDmic;
-
-/** Offset 0x0097 - HD-Audio Bluetooth
- Enable/Disable HD-Audio bluetooth. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 DspEndpointBluetooth;
-
-/** Offset 0x0098 - HD-Audio I2S SHK
- Enable/Disable HD-Audio I2S SHK. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 DspEndpointI2sSkp;
-
-/** Offset 0x0099 - HD-Audio I2S HP
- Enable/Disable HD-Audio I2S HP. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 DspEndpointI2sHp;
-
-/** Offset 0x009A - HD-Audio Controller Power Gating
- Enable/Disable HD-Audio Controller Power Gating. This option is deprecated.
- $EN_DIS
-**/
- UINT8 AudioCtlPwrGate;
-
-/** Offset 0x009B - HD-Audio ADSP Power Gating
- Enable/Disable HD-Audio ADSP Power Gating. This option is deprecated.
- $EN_DIS
-**/
- UINT8 AudioDspPwrGate;
-
-/** Offset 0x009C - HD-Audio CSME Memory Transfers
- Enable/Disable HD-Audio CSME Memory Transfers. 0:VC0(Default), 1:VC2.
- 0: VC0, 1: VC2
-**/
- UINT8 Mmt;
-
-/** Offset 0x009D - HD-Audio Host Memory Transfers
- Enable/Disable HD-Audio Host Memory Transfers. 0:VC0(Default), 1:VC2.
- 0: VC0, 1: VC2
-**/
- UINT8 Hmt;
-
-/** Offset 0x009E - HD-Audio Power Gating
- Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 HDAudioPwrGate;
-
-/** Offset 0x009F - HD-Audio Clock Gatingn
- Enable/Disable HD-Audio Clock Gating. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 HDAudioClkGate;
-
-/** Offset 0x00A0 - Bitmask of DSP Feature
- Set Bitmask of HD-Audio DSP Feature. 0x00000000(Default).
- [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]
- - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
- Intel WoV, 1: Windows Voice Activation
-**/
- UINT32 DspFeatureMask;
-
-/** Offset 0x00A4 - Bitmask of supported DSP Post-Processing Modules
- Set HD-Audio Bitmask of supported DSP Post-Processing Modules. 0x00000000(Default).
- [BIT0] - WoV, [BIT1] - BT Sideband, [BIT2] - Codec VAD, [BIT5] - BT Intel HFP, [BIT6]
- - BT Intel A2DP, [BIT7] - DSP based speech pre-processing disabled, [BIT8] - 0:
- Intel WoV, 1: Windows Voice Activation
-**/
- UINT32 DspPpModuleMask;
-
-/** Offset 0x00A8 - HD-Audio BIOS Configuration Lock Down
- Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable.
- This option is deprecated
- $EN_DIS
-**/
- UINT8 BiosCfgLockDown;
-
-/** Offset 0x00A9 - Enable High Precision Timer
- Enable/Disable Hpet. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 Hpet;
-
-/** Offset 0x00AA - Hpet Valid BDF Value
- Enable/Disable Hpet Valid BDF Value. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 HpetBdfValid;
-
-/** Offset 0x00AB - Bus Number of Hpet
- Completer ID of Bus Number of Hpet. Default = 0xFA(Default).
-**/
- UINT8 HpetBusNumber;
-
-/** Offset 0x00AC - Device Number of Hpet
- Completer ID of Device Number of Hpet. 0x1F(Default).
-**/
- UINT8 HpetDeviceNumber;
-
-/** Offset 0x00AD - Function Number of Hpet
- Completer ID of Function Number of Hpet. 0x00(Default).
-**/
- UINT8 HpetFunctionNumber;
-
-/** Offset 0x00AE - IoApic Valid BDF Value
- Enable/Disable IoApic Valid BDF Value. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 IoApicBdfValid;
-
-/** Offset 0x00AF - Bus Number of IoApic
- Completer ID of Bus Number of IoApic. 0xFA(Default).
-**/
- UINT8 IoApicBusNumber;
-
-/** Offset 0x00B0 - Device Number of IoApic
- Completer ID of Device Number of IoApic. 0x0F(Default).
-**/
- UINT8 IoApicDeviceNumber;
-
-/** Offset 0x00B1 - Function Number of IoApic
- Completer ID of Function Number of IoApic. 0x00(Default).
-**/
- UINT8 IoApicFunctionNumber;
-
-/** Offset 0x00B2 - IOAPIC Entry 24-119
- Enable/Disable IOAPIC Entry 24-119. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 IoApicEntry24_119;
-
-/** Offset 0x00B3 - IO APIC ID
- This member determines IOAPIC ID. 0x01(Default).
-**/
- UINT8 IoApicId;
-
-/** Offset 0x00B4 - IoApic Range
- Define address bits 19:12 for the IOxAPIC range. 0x00(Default).
-**/
- UINT8 IoApicRangeSelect;
-
-/** Offset 0x00B5 - ISH Controller
- Enable/Disable ISH Controller. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 IshEnable;
-
-/** Offset 0x00B6 - BIOS Interface Lock Down
- Enable/Disable BIOS Interface Lock Down bit to prevent writes to the Backup Control
- Register. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 BiosInterface;
-
-/** Offset 0x00B7 - Bios LockDown Enable
- Enable the BIOS Lock Enable (BLE) feature and set EISS bit. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 BiosLock;
-
-/** Offset 0x00B8 - SPI EISS Status
- Enable/Disable InSMM.STS (EISS) in SPI. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 SpiEiss;
-
-/** Offset 0x00B9 - BiosLock SWSMI Number
- This member describes the SwSmi value for Bios Lock. 0xA9(Default).
-**/
- UINT8 BiosLockSwSmiNumber;
-
-/** Offset 0x00BA - LPSS IOSF PMCTL S0ix Enable
- Enable/Disable LPSS IOSF Bridge PMCTL Register S0ix Bits. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 LPSS_S0ixEnable;
-
-/** Offset 0x00BB
-**/
- UINT8 UnusedUpdSpace0[1];
-
-/** Offset 0x00BC - LPSS I2C Clock Gating Configuration
- Enable/Disable LPSS I2C Clock Gating. 0:Disable, 1:Enable(Default).
-**/
- UINT8 I2cClkGateCfg[8];
-
-/** Offset 0x00C4 - PSS HSUART Clock Gating Configuration
- Enable/Disable LPSS HSUART Clock Gating. 0:Disable, 1:Enable(Default).
-**/
- UINT8 HsuartClkGateCfg[4];
-
-/** Offset 0x00C8 - LPSS SPI Clock Gating Configuration
- Enable/Disable LPSS SPI Clock Gating. 0:Disable, 1:Enable(Default).
-**/
- UINT8 SpiClkGateCfg[3];
-
-/** Offset 0x00CB - I2C Device 0
- Enable/Disable I2C Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 I2c0Enable;
-
-/** Offset 0x00CC - I2C Device 1
- Enable/Disable I2C Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 I2c1Enable;
-
-/** Offset 0x00CD - I2C Device 2
- Enable/Disable I2C Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 I2c2Enable;
-
-/** Offset 0x00CE - I2C Device 3
- Enable/Disable I2C Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 I2c3Enable;
-
-/** Offset 0x00CF - I2C Device 4
- Enable/Disable I2C Device 4. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 I2c4Enable;
-
-/** Offset 0x00D0 - I2C Device 5
- Enable/Disable I2C Device 5. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 I2c5Enable;
-
-/** Offset 0x00D1 - I2C Device 6
- Enable/Disable I2C Device 6. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 I2c6Enable;
-
-/** Offset 0x00D2 - I2C Device 7
- Enable/Disable I2C Device 7. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 I2c7Enable;
-
-/** Offset 0x00D3 - UART Device 0
- Enable/Disable UART Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 Hsuart0Enable;
-
-/** Offset 0x00D4 - UART Device 1
- Enable/Disable UART Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 Hsuart1Enable;
-
-/** Offset 0x00D5 - UART Device 2
- Enable/Disable UART Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 Hsuart2Enable;
-
-/** Offset 0x00D6 - UART Device 3
- Enable/Disable UART Device 3. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 Hsuart3Enable;
-
-/** Offset 0x00D7 - SPI UART Device 0
- Enable/Disable SPI Device 0. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 Spi0Enable;
-
-/** Offset 0x00D8 - SPI UART Device 1
- Enable/Disable SPI Device 1. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 Spi1Enable;
-
-/** Offset 0x00D9 - SPI UART Device 2
- Enable/Disable SPI Device 2. 0:Disabled, 1:PCI Mode(Default), 2:ACPI Mode.
- 0: Disabled, 1: PCI Mode, 2: ACPI Mode
-**/
- UINT8 Spi2Enable;
-
-/** Offset 0x00DA - OS Debug Feature
- Enable/Disable OS Debug Feature. 0:Disable(Default), 1: Enable.
- $EN_DIS
-**/
- UINT8 OsDbgEnable;
-
-/** Offset 0x00DB - DCI Feature
- Enable/Disable DCI Feature. 0:Disable(Default), 1: Enable.
- $EN_DIS
-**/
- UINT8 DciEn;
-
-/** Offset 0x00DC - UART Debug Base Address
- UART Debug Base Address. 0x00000000(Default).
-**/
- UINT32 Uart2KernelDebugBaseAddress;
-
-/** Offset 0x00E0 - Enable PCIE Clock Gating
- Enable/disable PCIE Clock Gating. 0:Enable, 1:Disable(Default).
- 0:Enable, 1:Disable
-**/
- UINT8 PcieClockGatingDisabled;
-
-/** Offset 0x00E1 - Enable PCIE Root Port 8xh Decode
- Enable/disable PCIE Root Port 8xh Decode. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 PcieRootPort8xhDecode;
-
-/** Offset 0x00E2 - PCIE 8xh Decode Port Index
- PCIE 8xh Decode Port Index. 0x00(Default).
-**/
- UINT8 Pcie8xhDecodePortIndex;
-
-/** Offset 0x00E3 - Enable PCIE Root Port Peer Memory Write
- Enable/disable PCIE root port peer memory write. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 PcieRootPortPeerMemoryWriteEnable;
-
-/** Offset 0x00E4 - PCIE SWSMI Number
- This member describes the SwSmi value for override PCIe ASPM table. 0xAA(Default).
-**/
- UINT8 PcieAspmSwSmiNumber;
-
-/** Offset 0x00E5
-**/
- UINT8 UnusedUpdSpace1[1];
-
-/** Offset 0x00E6 - PCI Express Root Port
- Control the PCI Express Root Port . 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRootPortEn[6];
-
-/** Offset 0x00EC - Hide PCIE Root Port Configuration Space
- Enable/disable Hide PCIE Root Port Configuration Space. 0:Disable(Default), 1:Enable.
-**/
- UINT8 PcieRpHide[6];
-
-/** Offset 0x00F2 - PCIE Root Port Slot Implement
- Enable/disable PCIE Root Port Slot Implement. 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRpSlotImplemented[6];
-
-/** Offset 0x00F8 - Hot Plug
- PCI Express Hot Plug Enable/Disable. 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRpHotPlug[6];
-
-/** Offset 0x00FE - PCIE PM SCI
- Enable/Disable PCI Express PME SCI. 0:Disable(Default), 1:Enable.
-**/
- UINT8 PcieRpPmSci[6];
-
-/** Offset 0x0104 - PCIE Root Port Extended Sync
- Enable/Disable PCIE Root Port Extended Sync. 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRpExtSync[6];
-
-/** Offset 0x010A - Transmitter Half Swing
- Transmitter Half Swing Enable/Disable. 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRpTransmitterHalfSwing[6];
-
-/** Offset 0x0110 - ACS
- Enable/Disable Access Control Services Extended Capability. 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRpAcsEnabled[6];
-
-/** Offset 0x0116 - Clock Request Support
- Enable/Disable CLKREQ# Support. 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRpClkReqSupported[6];
-
-/** Offset 0x011C - Configure CLKREQ Number
- Configure Root Port CLKREQ Number if CLKREQ is supported. Default=0x04, 0x05, 0x00,
- 0x01, 0x02, 0x03.
-**/
- UINT8 PcieRpClkReqNumber[6];
-
-/** Offset 0x0122 - CLKREQ# Detection
- Enable/Disable CLKREQ# Detection Probe. 0: Disable(Default), 1: Enable.
-**/
- UINT8 PcieRpClkReqDetect[6];
-
-/** Offset 0x0128 - Advanced Error Reporting
- Enable/Disable Advanced Error Reporting. 0: Disable(Default), 1: Enable.
-**/
- UINT8 AdvancedErrorReporting[6];
-
-/** Offset 0x012E - PME Interrupt
- Enable/Disable PME Interrupt. 0: Disable(Default), 1: Enable.
-**/
- UINT8 PmeInterrupt[6];
-
-/** Offset 0x0134 - URR
- PCI Express Unsupported Request Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
-**/
- UINT8 UnsupportedRequestReport[6];
-
-/** Offset 0x013A - FER
- PCI Express Device Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
-**/
- UINT8 FatalErrorReport[6];
-
-/** Offset 0x0140 - NFER
- PCI Express Device Non-Fatal Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
-**/
- UINT8 NoFatalErrorReport[6];
-
-/** Offset 0x0146 - CER
- PCI Express Device Correctable Error Reporting Enable/Disable. 0:Disable(Default), 1:Enable.
-**/
- UINT8 CorrectableErrorReport[6];
-
-/** Offset 0x014C - SEFE
- Root PCI Express System Error on Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
-**/
- UINT8 SystemErrorOnFatalError[6];
-
-/** Offset 0x0152 - SENFE
- Root PCI Express System Error on Non-Fatal Error Enable/Disable. 0:Disable(Default), 1:Enable.
-**/
- UINT8 SystemErrorOnNonFatalError[6];
-
-/** Offset 0x0158 - SECE
- Root PCI Express System Error on Correctable Error Enable/Disable. 0:Disable(Default), 1:Enable.
-**/
- UINT8 SystemErrorOnCorrectableError[6];
-
-/** Offset 0x015E - PCIe Speed
- Configure PCIe Speed. 0:Auto(Default), 1:Gen1, 2:Gen2, 3:Gen3.
-**/
- UINT8 PcieRpSpeed[6];
-
-/** Offset 0x0164 - Physical Slot Number
- Physical Slot Number for PCIE Root Port. Default=0x00, 0x01, 0x02, 0x03, 0x04, 0x05.
-**/
- UINT8 PhysicalSlotNumber[6];
-
-/** Offset 0x016A - CTO
- Enable/Disable PCI Express Completion Timer TO . 0:Disable(Default), 1:Enable.
-**/
- UINT8 PcieRpCompletionTimeout[6];
-
-/** Offset 0x0170 - PTM Support
- Enable/Disable PTM Support. 0:Disable(Default), 1:Enable.
-**/
- UINT8 PtmEnable[6];
-
-/** Offset 0x0176 - ASPM
- PCI Express Active State Power Management settings. 0:Disable, 1:L0s, 2:L1, 3:L0sL1,
- 4:Auto(Default).
-**/
- UINT8 PcieRpAspm[6];
-
-/** Offset 0x017C - L1 Substates
- PCI Express L1 Substates settings. 0:Disable, 1:L1.1, 2:L1.2, 3:L1.1 & L1.2(Default).
-**/
- UINT8 PcieRpL1Substates[6];
-
-/** Offset 0x0182 - PCH PCIe LTR
- PCH PCIE Latency Reporting Enable/Disable. 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRpLtrEnable[6];
-
-/** Offset 0x0188 - PCIE LTR Lock
- PCIE LTR Configuration Lock. 0:Disable(Default), 1:Enable.
-**/
- UINT8 PcieRpLtrConfigLock[6];
-
-/** Offset 0x018E - PME_B0_S5 Disable bit
- PME_B0_S5_DIS bit in the General PM Configuration B (GEN_PMCON_B) register. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 PmeB0S5Dis;
-
-/** Offset 0x018F - PCI Clock Run
- This member describes whether or not the PCI ClockRun feature of SC should be enabled.
- 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 PciClockRun;
-
-/** Offset 0x0190 - Enable/Disable Timer 8254 Clock Setting
- Enable/Disable Timer 8254 Clock. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 Timer8254ClkSetting;
-
-/** Offset 0x0191 - Chipset SATA
- Enables or Disables the Chipset SATA Controller. The Chipset SATA controller supports
- the 2 black internal SATA ports (up to 3Gb/s supported per port). 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 EnableSata;
-
-/** Offset 0x0192 - SATA Mode Selection
- Determines how SATA controller(s) operate. 0:AHCI(Default), 1:RAID.
- 0:AHCI, 1:RAID
-**/
- UINT8 SataMode;
-
-/** Offset 0x0193 - Aggressive LPM Support
- Enable PCH to aggressively enter link power state. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 SataSalpSupport;
-
-/** Offset 0x0194 - SATA Power Optimization
- Enable SATA Power Optimizer on SC side. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 SataPwrOptEnable;
-
-/** Offset 0x0195 - eSATA Speed Limit
- Enable/Disable eSATA Speed Limit. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 eSATASpeedLimit;
-
-/** Offset 0x0196 - SATA Speed Limit
- SATA Speed Limit. 0h:ScSataSpeed(Default), 1h:1.5Gb/s(Gen 1), 2h:3Gb/s(Gen 2), 3h:6Gb/s(Gen 3).
- 0:Default, 1: 1.5 Gb/s (Gen 1), 2: 3 Gb/s(Gen 2), 3: 6 Gb/s (Gen 1)
-**/
- UINT8 SpeedLimit;
-
-/** Offset 0x0197
-**/
- UINT8 UnusedUpdSpace2[1];
-
-/** Offset 0x0198 - SATA Port
- Enable or Disable SATA Port. 0:Disable, 1:Enable(Default).
-**/
- UINT8 SataPortsEnable[2];
-
-/** Offset 0x019A - SATA Port DevSlp
- Enable/Disable SATA Port DevSlp. Board rework for LP needed before enable. 0:Disable(Default), 1:Enable.
-**/
- UINT8 SataPortsDevSlp[2];
-
-/** Offset 0x019C - SATA Port HotPlug
- Enable/Disable SATA Port Hotplug . 0:Disable(Default), 1:Enable.
-**/
- UINT8 SataPortsHotPlug[2];
-
-/** Offset 0x019E - Mechanical Presence Switch
- Controls reporting if this port has an Mechanical Presence Switch.\n
- Note:Requires hardware support. 0:Disable, 1:Enable(Default).
-**/
- UINT8 SataPortsInterlockSw[2];
-
-/** Offset 0x01A0 - External SATA Ports
- Enable/Disable External SATA Ports. 0:Disable(Default), 1:Enable.
-**/
- UINT8 SataPortsExternal[2];
-
-/** Offset 0x01A2 - Spin Up Device
- Enable/Disable device spin up at boot on selected Sata Ports. 0:Disable(Default), 1:Enable.
-**/
- UINT8 SataPortsSpinUp[2];
-
-/** Offset 0x01A4 - SATA Solid State
- Identify the SATA port is connected to Solid State Drive or Hard Disk Drive. 0:Hard
- Disk Drive(Default), 1:Solid State Drive.
-**/
- UINT8 SataPortsSolidStateDrive[2];
-
-/** Offset 0x01A6 - DITO Configuration
- Enable/Disable DITO Configuration. 0:Disable(Default), 1:Enable.
-**/
- UINT8 SataPortsEnableDitoConfig[2];
-
-/** Offset 0x01A8 - DM Value
- DM Value. 0:Minimum, 0x0F:Maximum(Default).
-**/
- UINT8 SataPortsDmVal[2];
-
-/** Offset 0x01AA
-**/
- UINT8 UnusedUpdSpace3[2];
-
-/** Offset 0x01AC - DITO Value
- DEVSLP Idle Timeout Value. 0:Minimum, 0x03FF:Maximum, 0x0271(Default).
-**/
- UINT16 SataPortsDitoVal[2];
-
-/** Offset 0x01B0 - Subsystem Vendor ID
- Subsystem Vendor ID. 0x8086(Default).
-**/
- UINT16 SubSystemVendorId;
-
-/** Offset 0x01B2 - Subsystem ID
- Subsystem ID. 0x7270(Default).
-**/
- UINT16 SubSystemId;
-
-/** Offset 0x01B4 - CRIDSettings
- PMC CRID setting. 0:Disable(Default), 1:CRID_1, 2:CRID_2, 3:CRID_3.
-**/
- UINT8 CRIDSettings;
-
-/** Offset 0x01B5 - ResetSelect
- ResetSelect. 0x6:warm reset(Default), 0xE:cold reset.
-**/
- UINT8 ResetSelect;
-
-/** Offset 0x01B6 - SD Card Support (D27:F0)
- Enable/Disable SD Card Support. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 SdcardEnabled;
-
-/** Offset 0x01B7 - SeMMC Support (D28:F0)
- Enable/Disable eMMC Support. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 eMMCEnabled;
-
-/** Offset 0x01B8 - eMMC Max Speed
- Select the eMMC max Speed allowed. 0:HS400(Default), 1:HS200, 2:DDR50.
- 0:HS400, 1: HS200, 2:DDR50
-**/
- UINT8 eMMCHostMaxSpeed;
-
-/** Offset 0x01B9 - UFS Support (D29:F0)
- Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 UfsEnabled;
-
-/** Offset 0x01BA - SDIO Support (D30:F0)
- Enable/Disable SDIO Support. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 SdioEnabled;
-
-/** Offset 0x01BB - GPP Lock Feature
- Enable/Disable GPP lock. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 GppLock;
-
-/** Offset 0x01BC - Serial IRQ
- Enable/Disable Serial IRQ. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 SirqEnable;
-
-/** Offset 0x01BD - Serial IRQ Mode
- Serial IRQ Mode Selection. 0:Quiet mode(Default), 1:Continuous mode.
- $EN_DIS
-**/
- UINT8 SirqMode;
-
-/** Offset 0x01BE - Start Frame Pulse Width
- Start Frame Pulse Width Value. 0:ScSfpw4Clk(Default), 1: ScSfpw6Clk, 2:ScSfpw8Clk.
- 0:ScSfpw4Clk, 1:ScSfpw6Clk, 2:ScSfpw8Clk
-**/
- UINT8 StartFramePulse;
-
-/** Offset 0x01BF - Enable SMBus
- Enable/disable SMBus controller. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 SmbusEnable;
-
-/** Offset 0x01C0 - SMBus ARP Support
- Enable/disable SMBus ARP Support. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 ArpEnable;
-
-/** Offset 0x01C1
-**/
- UINT8 UnusedUpdSpace4;
-
-/** Offset 0x01C2 - SMBus Table Elements
- The number of elements in the Reserved SMBus Address Table. 0x0080(Default).
-**/
- UINT16 NumRsvdSmbusAddresses;
-
-/** Offset 0x01C4 - Reserved SMBus Address Table
- Array of addresses reserved for non-ARP-capable SMBus devices. 0x00(Default).
-**/
- UINT8 RsvdSmbusAddressTable[128];
-
-/** Offset 0x0244 - XHCI Disable Compliance Mode
- Options to disable XHCI Link Compliance Mode. Default is FALSE to not disable Compliance
- Mode. Set TRUE to disable Compliance Mode. 0:FALSE(Default), 1:True.
- $EN_DIS
-**/
- UINT8 DisableComplianceMode;
-
-/** Offset 0x0245 - USB Per-Port Control
- Control each of the USB ports enable/disable. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 UsbPerPortCtl;
-
-/** Offset 0x0246 - xHCI Mode
- Mode of operation of xHCI controller. 0:Disable, 1:Enable, 2:Auto(Default)
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Usb30Mode;
-
-/** Offset 0x0247
-**/
- UINT8 UnusedUpdSpace5[1];
-
-/** Offset 0x0248 - Enable USB2 ports
- Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on. 0x01(Default).
-**/
- UINT8 PortUsb20Enable[8];
-
-/** Offset 0x0250 - USB20 Over Current Pin
- Over Current Pin number of USB 2.0 Port. 0x00(Default).
-**/
- UINT8 PortUs20bOverCurrentPin[8];
-
-/** Offset 0x0258 - XDCI Support
- Enable/Disable XDCI. 0:Disable, 1:PCI_Mode(Default), 2:ACPI_mode.
- 0:Disable, 1:PCI_Mode, 2:ACPI_mode
-**/
- UINT8 UsbOtg;
-
-/** Offset 0x0259 - Enable XHCI HSIC Support
- Enable/Disable USB HSIC1. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 HsicSupportEnable;
-
-/** Offset 0x025A - Enable USB3 ports
- Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on. 0x01(Default).
-**/
- UINT8 PortUsb30Enable[6];
-
-/** Offset 0x0260 - USB20 Over Current Pin
- Over Current Pin number of USB 3.0 Port. 0x01(Default).
-**/
- UINT8 PortUs30bOverCurrentPin[6];
-
-/** Offset 0x0266 - Enable XHCI SSIC Support
- Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for
- port1. 0x00(Default).
-**/
- UINT8 SsicPortEnable[2];
-
-/** Offset 0x0268 - SSIC Dlane PowerGating
- Enable/Disable SSIC Data lane Power Gating. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT16 DlanePwrGating;
-
-/** Offset 0x026A - VT-d
- Enable/Disable VT-d. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 VtdEnable;
-
-/** Offset 0x026B - SMI Lock bit
- Enable/Disable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0:Disable,
- 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 LockDownGlobalSmi;
-
-/** Offset 0x026C - HDAudio Delay Timer
- The delay timer after Azalia reset. 0x012C(Default).
-**/
- UINT16 ResetWaitTimer;
-
-/** Offset 0x026E - RTC Lock Bits
- Enable/Disable RTC Lock Bits. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 RtcLock;
-
-/** Offset 0x026F - SATA Test Mode Selection
- Enable/Disable SATA Test Mode. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT8 SataTestMode;
-
-/** Offset 0x0270 - XHCI SSIC RATE
- Set XHCI SSIC1 Rate to A Series or B Series. 1:A Series(Default), 2:B Series.
-**/
- UINT8 SsicRate[2];
-
-/** Offset 0x0272 - SMBus Dynamic Power Gating
- Enable/Disable SMBus dynamic power gating. 0:Disable(Default), 1:Enable.
- $EN_DIS
-**/
- UINT16 DynamicPowerGating;
-
-/** Offset 0x0274 - Max Snoop Latency
- Latency Tolerance Reporting Max Snoop Latency. 0x0000(Default).
-**/
- UINT16 PcieRpLtrMaxSnoopLatency[6];
-
-/** Offset 0x0280 - Snoop Latency Override
- Snoop Latency Override for PCH PCIE. \n
- Disabled:Disable override.\n
- Manual:Manually enter override values.\n
- Auto:Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
-**/
- UINT8 PcieRpSnoopLatencyOverrideMode[6];
-
-/** Offset 0x0286
-**/
- UINT8 UnusedUpdSpace6[2];
-
-/** Offset 0x0288 - Snoop Latency Value
- LTR Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
-**/
- UINT16 PcieRpSnoopLatencyOverrideValue[6];
-
-/** Offset 0x0294 - Snoop Latency Multiplier
- LTR Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default), 3:32768ns,
- 4:1048576ns, 5:33554432ns.
-**/
- UINT8 PcieRpSnoopLatencyOverrideMultiplier[6];
-
-/** Offset 0x029A - Skip Multi-Processor Initialization
- When this is skipped, boot loader must initialize processors before SilicionInit
- API. 0: Initialize(Default), <b>1: Skip
- $EN_DIS
-**/
- UINT8 SkipMpInit;
-
-/** Offset 0x029B - DCI Auto Detect
- Enable/disable DCI AUTO mode. Enabled(Default).
- $EN_DIS
-**/
- UINT8 DciAutoDetect;
-
-/** Offset 0x029C - Max Non-Snoop Latency
- Latency Tolerance Reporting, Max Non-Snoop Latency. 0x0000(Default).
-**/
- UINT16 PcieRpLtrMaxNonSnoopLatency[6];
-
-/** Offset 0x02A8 - Non Snoop Latency Override
- Non Snoop Latency Override for PCH PCIE. \n
- Disabled:Disable override.\n
- Manual:Manually enter override values.\n
- Auto: Maintain default BIOS flow. 0:Disable, 1:Enable, 2:Auto(Default).
-**/
- UINT8 PcieRpNonSnoopLatencyOverrideMode[6];
-
-/** Offset 0x02AE - Halt and Lock TCO Timer
- Halt and Lock the TCO Timer (Watchdog).
- 0:No, 1:Yes (default)
-**/
- UINT8 TcoTimerHaltLock;
-
-/** Offset 0x02AF - Power Button Override Period
- specifies how long will PMC wait before initiating a global reset. 000b-4s(default),
- 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.)
- 0x0:4s, 0x1:6s, 0x2:8s, 0x3:10s, 0x4:12s, 0x5:14s
-**/
- UINT8 PwrBtnOverridePeriod;
-
-/** Offset 0x02B0 - Non Snoop Latency Value
- LTR Non Snoop Latency value of PCH PCIE. 0:Minimum, 0x03FF:Maximum, 0x003C(Default).
-**/
- UINT16 PcieRpNonSnoopLatencyOverrideValue[6];
-
-/** Offset 0x02BC - Non Snoop Latency Multiplier
- LTR Non Snoop Latency Multiplier of PCH PCIE. 0:1ns, 1:32ns, 2:1024ns(Default),
- 3:32768ns, 4:1048576ns, 5:33554432ns.
-**/
- UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[6];
-
-/** Offset 0x02C2 - PCIE Root Port Slot Power Limit Scale
- Specifies scale used for slot power limit value. 0x00(Default).
-**/
- UINT8 PcieRpSlotPowerLimitScale[6];
-
-/** Offset 0x02C8 - PCIE Root Port Slot Power Limit Value
- Specifies upper limit on power supplie by slot. 0x00(Default).
-**/
- UINT8 PcieRpSlotPowerLimitValue[6];
-
-/** Offset 0x02CE - Power Button Native Mode Disable
- Disable power button native mode, when 1, this will result in the PMC logic constantly
- seeing the power button as de-asserted. 0 (default))
- $EN_DIS
-**/
- UINT8 DisableNativePowerButton;
-
-/** Offset 0x02CF - Power Button Debounce Mode
- Enable interrupt when PWRBTN# is asserted. 0:Disabled, 1:Enabled(default)
- $EN_DIS
-**/
- UINT8 PowerButterDebounceMode;
-
-/** Offset 0x02D0 - SDIO_TX_CMD_DLL_CNTL
- SDIO_TX_CMD_DLL_CNTL. 0x505(Default).
-**/
- UINT32 SdioTxCmdCntl;
-
-/** Offset 0x02D4 - SDIO_TX_DATA_DLL_CNTL1
- SDIO_TX_DATA_DLL_CNTL1. 0xE(Default).
-**/
- UINT32 SdioTxDataCntl1;
-
-/** Offset 0x02D8 - SDIO_TX_DATA_DLL_CNTL2
- SDIO_TX_DATA_DLL_CNTL2. 0x22272828(Default).
-**/
- UINT32 SdioTxDataCntl2;
-
-/** Offset 0x02DC - SDIO_RX_CMD_DATA_DLL_CNTL1
- SDIO_RX_CMD_DATA_DLL_CNTL1. 0x16161616(Default).
-**/
- UINT32 SdioRxCmdDataCntl1;
-
-/** Offset 0x02E0 - SDIO_RX_CMD_DATA_DLL_CNTL2
- SDIO_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
-**/
- UINT32 SdioRxCmdDataCntl2;
-
-/** Offset 0x02E4 - SDCARD_TX_CMD_DLL_CNTL
- SDCARD_TX_CMD_DLL_CNTL. 0x505(Default).
-**/
- UINT32 SdcardTxCmdCntl;
-
-/** Offset 0x02E8 - SDCARD_TX_DATA_DLL_CNTL1
- SDCARD_TX_DATA_DLL_CNTL1. 0xA13(Default).
-**/
- UINT32 SdcardTxDataCntl1;
-
-/** Offset 0x02EC - SDCARD_TX_DATA_DLL_CNTL2
- SDCARD_TX_DATA_DLL_CNTL2. 0x24242828(Default).
-**/
- UINT32 SdcardTxDataCntl2;
-
-/** Offset 0x02F0 - SDCARD_RX_CMD_DATA_DLL_CNTL1
- SDCARD_RX_CMD_DATA_DLL_CNTL1. 0x73A3637(Default).
-**/
- UINT32 SdcardRxCmdDataCntl1;
-
-/** Offset 0x02F4 - SDCARD_RX_STROBE_DLL_CNTL
- SDCARD_RX_STROBE_DLL_CNTL. 0x0(Default).
-**/
- UINT32 SdcardRxStrobeCntl;
-
-/** Offset 0x02F8 - SDCARD_RX_CMD_DATA_DLL_CNTL2
- SDCARD_RX_CMD_DATA_DLL_CNTL2. 0x10000(Default).
-**/
- UINT32 SdcardRxCmdDataCntl2;
-
-/** Offset 0x02FC - EMMC_TX_CMD_DLL_CNTL
- EMMC_TX_CMD_DLL_CNTL. 0x505(Default).
-**/
- UINT32 EmmcTxCmdCntl;
-
-/** Offset 0x0300 - EMMC_TX_DATA_DLL_CNTL1
- EMMC_TX_DATA_DLL_CNTL1. 0xC11(Default).
-**/
- UINT32 EmmcTxDataCntl1;
-
-/** Offset 0x0304 - EMMC_TX_DATA_DLL_CNTL2
- EMMC_TX_DATA_DLL_CNTL2. 0x1C2A2927(Default).
-**/
- UINT32 EmmcTxDataCntl2;
-
-/** Offset 0x0308 - EMMC_RX_CMD_DATA_DLL_CNTL1
- EMMC_RX_CMD_DATA_DLL_CNTL1. 0x000D162F(Default).
-**/
- UINT32 EmmcRxCmdDataCntl1;
-
-/** Offset 0x030C - EMMC_RX_STROBE_DLL_CNTL
- EMMC_RX_STROBE_DLL_CNTL. 0x0a0a(Default).
-**/
- UINT32 EmmcRxStrobeCntl;
-
-/** Offset 0x0310 - EMMC_RX_CMD_DATA_DLL_CNTL2
- EMMC_RX_CMD_DATA_DLL_CNTL2. 0x1003b(Default).
-**/
- UINT32 EmmcRxCmdDataCntl2;
-
-/** Offset 0x0314 - EMMC_MASTER_DLL_CNTL
- EMMC_MASTER_DLL_CNTL. 0x001(Default).
-**/
- UINT32 EmmcMasterSwCntl;
-
-/** Offset 0x0318 - PCIe Selectable De-emphasis
- When the Link is operating at 5.0 GT/s speed, this bit selects the level of de-emphasis
- for an Upstream component. 1b:-3.5 dB 0b:-6 dB. 0:Disable, 1:Enable(Default).
-**/
- UINT8 PcieRpSelectableDeemphasis[6];
-
-/** Offset 0x031E - Monitor Mwait Enable
- Enable/Disable Monitor Mwait. For Windows* OS, this should be Enabled. For Linux
- based OS, this should be Disabled. 0:Disable, 1:Enable(Default).
- $EN_DIS
-**/
- UINT8 MonitorMwaitEnable;
-
-/** Offset 0x031F - Universal Audio Architecture compliance for DSP enabled system
- 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
- driver or SST driver supported).
- $EN_DIS
-**/
- UINT8 HdAudioDspUaaCompliance;
-
-/** Offset 0x0320 - IRQ Interrupt Polarity Control
- Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low
-**/
- UINT32 IPC[4];
-
-/** Offset 0x0330 - Disable ModPHY dynamic power gate
- Disable ModPHY dynamic power gate for the specific SATA port.
-**/
- UINT8 SataPortsDisableDynamicPg[2];
-
-/** Offset 0x0332 - Init CPU during S3 resume
- 0: Do not initialize CPU during S3 resume. 1: Initialize CPU during S3 resume.
- $EN_DIS
-**/
- UINT8 InitS3Cpu;
-
-/** Offset 0x0333 - Skip P-unit Initialization
- When this is skipped, boot loader must initialize P-unit before SilicionInit API.
- 0: Initialize(Default), 1: Skip
- $EN_DIS
-**/
- UINT8 SkipPunitInit;
-
-/** Offset 0x0334
-**/
- UINT8 UnusedUpdSpace7[4];
-
-/** Offset 0x0338 - PerPort Half Bit Pre-emphasis
- PerPort Half Bit Pre-emphasis. Value of register USB2_PER_PORT_PPX [14]
-**/
- UINT8 PortUsb20PerPortTxPeHalf[8];
-
-/** Offset 0x0340 - PerPort HS Pre-emphasis Bias
- PerPort HS Pre-emphasis Bias. Value of register USB2_PER_PORT_PPX [13:11]
-**/
- UINT8 PortUsb20PerPortPeTxiSet[8];
-
-/** Offset 0x0348 - PerPort HS Transmitter Bias
- PerPort HS Transmitter Bias. Value of register USB2_PER_PORT_PPX [10:8]
-**/
- UINT8 PortUsb20PerPortTxiSet[8];
-
-/** Offset 0x0350 - Select the skew direction for HS transition
- Select the skew direction for HS transition. Value of register USB2_PER_PORT_2_PPX [25]
-**/
- UINT8 PortUsb20HsSkewSel[8];
-
-/** Offset 0x0358 - Per Port HS Transmitter Emphasis
- Per Port HS Transmitter Emphasis. Value of register USB2_PER_PORT_2_PPX [24:23]
-**/
- UINT8 PortUsb20IUsbTxEmphasisEn[8];
-
-/** Offset 0x0360 - PerPort HS Receiver Bias
- PerPort HS Receiver Bias. Value of register USB2_PER_PORT_2_PPX [19:17]
-**/
- UINT8 PortUsb20PerPortRXISet[8];
-
-/** Offset 0x0368 - Delay/skew's strength control for HS driver
- Delay/skew's strength control for HS driver. Value of register USB2_PER_PORT_2_PPX [1:0]
-**/
- UINT8 PortUsb20HsNpreDrvSel[8];
-
-/** Offset 0x0370
-**/
- UINT8 ReservedFspsUpd[16];
-} FSP_S_CONFIG;
-
-/** Fsp S UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSP_S_CONFIG FspsConfig;
-
-/** Offset 0x0380
-**/
- UINT8 UnusedUpdSpace8[46];
-
-/** Offset 0x03AE
-**/
- UINT16 UpdTerminator;
-} FSPS_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
deleted file mode 100644
index fca01e94bf..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FirmwareVersionInfoHob.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/** @file
- Header file for Firmware Version Information
-
- Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available under
- the terms and conditions of the BSD License which accompanies this distribution.
- The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
-#define _FIRMWARE_VERSION_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack(1)
-///
-/// Firmware Version Structure
-///
-typedef struct {
- UINT8 MajorVersion;
- UINT8 MinorVersion;
- UINT8 Revision;
- UINT16 BuildNumber;
-} FIRMWARE_VERSION;
-
-///
-/// Firmware Version Information Structure
-///
-typedef struct {
- UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
- UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
- FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
-} FIRMWARE_VERSION_INFO;
-
-#ifndef __SMBIOS_STANDARD_H__
-///
-/// The Smbios structure header.
-///
-typedef struct {
- UINT8 Type;
- UINT8 Length;
- UINT16 Handle;
-} SMBIOS_STRUCTURE;
-#endif
-
-///
-/// Firmware Version Information HOB Structure
-///
-typedef struct {
- EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
- SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
- UINT8 Count; ///< Offset 28 Number of FVI elements included.
-///
-/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
-///
-} FIRMWARE_VERSION_INFO_HOB;
-#pragma pack()
-
-#endif // _FIRMWARE_VERSION_INFO_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
deleted file mode 100644
index ae258146c9..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspUpd.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPUPD_H__
-#define __FSPUPD_H__
-
-#include <FspEas.h>
-
-#pragma pack(1)
-
-#define FSPT_UPD_SIGNATURE 0x545F4450554C4643 /* 'CFLUPD_T' */
-
-#define FSPM_UPD_SIGNATURE 0x4D5F4450554C4643 /* 'CFLUPD_M' */
-
-#define FSPS_UPD_SIGNATURE 0x535F4450554C4643 /* 'CFLUPD_S' */
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
deleted file mode 100644
index 5a1580cb3c..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspmUpd.h
+++ /dev/null
@@ -1,2839 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-#include <MemInfoHob.h>
-
-///
-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
-///
-typedef struct {
- UINT8 Revision; ///< Chipset Init Info Revision
- UINT8 Rsvd[3]; ///< Reserved
- UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
- UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
-} CHIPSET_INIT_INFO;
-
-
-/** Fsp M Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Platform Reserved Memory Size
- The minimum platform memory size required to pass control into DXE
-**/
- UINT64 PlatformMemorySize;
-
-/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0
- Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
-**/
- UINT32 MemorySpdPtr00;
-
-/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1
- Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
-**/
- UINT32 MemorySpdPtr01;
-
-/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0
- Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
-**/
- UINT32 MemorySpdPtr10;
-
-/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1
- Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
-**/
- UINT32 MemorySpdPtr11;
-
-/** Offset 0x0058 - SPD Data Length
- Length of SPD Data
- 0x100:256 Bytes, 0x200:512 Bytes
-**/
- UINT16 MemorySpdDataLen;
-
-/** Offset 0x005A - Dq Byte Map CH0
- Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
-**/
- UINT8 DqByteMapCh0[12];
-
-/** Offset 0x0066 - Dq Byte Map CH1
- Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
-**/
- UINT8 DqByteMapCh1[12];
-
-/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0
- Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
-**/
- UINT8 DqsMapCpu2DramCh0[8];
-
-/** Offset 0x007A - Dqs Map CPU to DRAM CH 1
- Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
-**/
- UINT8 DqsMapCpu2DramCh1[8];
-
-/** Offset 0x0082 - RcompResister settings
- Indicates RcompReister settings: CNL - 0's means MRC auto configured based on Design
- Guidelines, otherwise input an Ohmic value per segment. CFL will need to provide
- the appropriate values.
-**/
- UINT16 RcompResistor[3];
-
-/** Offset 0x0088 - RcompTarget settings
- RcompTarget settings: CNL - 0's mean MRC auto configured based on Design Guidelines,
- otherwise input an Ohmic value per segment. CFL will need to provide the appropriate values.
-**/
- UINT16 RcompTarget[5];
-
-/** Offset 0x0092 - Dqs Pins Interleaved Setting
- Indicates DqPinsInterleaved setting: board-dependent
- $EN_DIS
-**/
- UINT8 DqPinsInterleaved;
-
-/** Offset 0x0093 - VREF_CA
- CA Vref routing: board-dependent
- 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
- 2:VREF_CA to CH_A and VREF_DQ_B to CH_B
-**/
- UINT8 CaVrefConfig;
-
-/** Offset 0x0094 - Smram Mask
- The SMM Regions AB-SEG and/or H-SEG reserved
- 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
-**/
- UINT8 SmramMask;
-
-/** Offset 0x0095 - MRC Fast Boot
- Enables/Disable the MRC fast path thru the MRC
- $EN_DIS
-**/
- UINT8 MrcFastBoot;
-
-/** Offset 0x0096 - Rank Margin Tool per Task
- This option enables the user to execute Rank Margin Tool per major training step
- in the MRC.
- $EN_DIS
-**/
- UINT8 RmtPerTask;
-
-/** Offset 0x0097 - Training Trace
- This option enables the trained state tracing feature in MRC. This feature will
- print out the key training parameters state across major training steps.
- $EN_DIS
-**/
- UINT8 TrainTrace;
-
-/** Offset 0x0098 - Intel Enhanced Debug
- Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
- 0 : Disable, 0x400000 : Enable
-**/
- UINT32 IedSize;
-
-/** Offset 0x009C - Tseg Size
- Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
- 0x0400000:4MB, 0x01000000:16MB
-**/
- UINT32 TsegSize;
-
-/** Offset 0x00A0 - MMIO Size
- Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
-**/
- UINT16 MmioSize;
-
-/** Offset 0x00A2 - Probeless Trace
- Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
- This also requires IED to be enabled.
- $EN_DIS
-**/
- UINT8 ProbelessTrace;
-
-/** Offset 0x00A3 - GDXC IOT SIZE
- Size of IOT and MOT is in 8 MB chunks
-**/
- UINT8 GdxcIotSize;
-
-/** Offset 0x00A4 - GDXC MOT SIZE
- Size of IOT and MOT is in 8 MB chunks
-**/
- UINT8 GdxcMotSize;
-
-/** Offset 0x00A5 - Enable SMBus
- Enable/disable SMBus controller.
- $EN_DIS
-**/
- UINT8 SmbusEnable;
-
-/** Offset 0x00A6 - Spd Address Tabl
- Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
- if SPD Address is 00
-**/
- UINT8 SpdAddressTable[4];
-
-/** Offset 0x00AA - Platform Debug Consent
- To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
- Enabling this BIOS option may alter the default value of other debug-related BIOS
- options. Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC]
- have the same setting
- 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC),
- 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC)
-**/
- UINT8 PlatformDebugConsent;
-
-/** Offset 0x00AB - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
- This BIOS option enables kernel and platform debug for USB3 interface over a UFP
- Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
- 0:Disabled, 1:Enabled, 2:No Change
-**/
- UINT8 DciUsb3TypecUfpDbg;
-
-/** Offset 0x00AC - PCH Trace Hub Mode
- Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
- if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
- 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
-**/
- UINT8 PchTraceHubMode;
-
-/** Offset 0x00AD - PCH Trace Hub Memory Region 0 buffer Size
- Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
- 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
- 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
-**/
- UINT8 PchTraceHubMemReg0Size;
-
-/** Offset 0x00AE - PCH Trace Hub Memory Region 1 buffer Size
- Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
- 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
- 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
-**/
- UINT8 PchTraceHubMemReg1Size;
-
-/** Offset 0x00AF - PchPreMemRsvd
- Reserved for PCH Pre-Mem Reserved
- $EN_DIS
-**/
- UINT8 PchPreMemRsvd[9];
-
-/** Offset 0x00B8 - Internal Graphics Pre-allocated Memory
- Size of memory preallocated for internal graphics.
- 0x00:0 MB, 0x01:32 MB, 0x02:64 MB
-**/
- UINT8 IgdDvmt50PreAlloc;
-
-/** Offset 0x00B9 - Internal Graphics
- Enable/disable internal graphics.
- $EN_DIS
-**/
- UINT8 InternalGfx;
-
-/** Offset 0x00BA - Aperture Size
- Select the Aperture Size.
- 0:128 MB, 1:256 MB, 2:512 MB
-**/
- UINT8 ApertureSize;
-
-/** Offset 0x00BB - Board Type
- MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
- Halo, 7=UP Server
- 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
-**/
- UINT8 UserBd;
-
-/** Offset 0x00BC - SA GV
- System Agent dynamic frequency support and when enabled memory will be training
- at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
- 2=FixedHigh, and 3=Enabled.
- 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
-**/
- UINT8 SaGv;
-
-/** Offset 0x00BD
-**/
- UINT8 UnusedUpdSpace0;
-
-/** Offset 0x00BE - DDR Frequency Limit
- Maximum Memory Frequency Selections in Mhz. Valid values should match the refclk,
- i.e. divide by 133 or 100
- 1067:1067, 1333:1333, 1400:1400, 1600:1600, 1800:1800, 1867:1867, 2000:2000, 2133:2133,
- 2200:2200, 2400:2400, 2600:2600, 2667:2667, 2800:2800, 2933:2933, 3000:3000, 3200:3200, 0:Auto
-**/
- UINT16 DdrFreqLimit;
-
-/** Offset 0x00C0 - Low Frequency
- SAGV Low Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
- 2400, 2667, 2933 and 0 for Auto.
- 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
-**/
- UINT16 FreqSaGvLow;
-
-/** Offset 0x00C2 - Mid Frequency
- SAGV Mid Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, 2133,
- 2400, 2667, 2933 and 0 for Auto.
- 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
-**/
- UINT16 FreqSaGvMid;
-
-/** Offset 0x00C4 - Rank Margin Tool
- Enable/disable Rank Margin Tool.
- $EN_DIS
-**/
- UINT8 RMT;
-
-/** Offset 0x00C5 - Channel A DIMM Control
- Channel A DIMM Control Support - Enable or Disable Dimms on Channel A.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmChannel0;
-
-/** Offset 0x00C6 - Channel B DIMM Control
- Channel B DIMM Control Support - Enable or Disable Dimms on Channel B.
- 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs
-**/
- UINT8 DisableDimmChannel1;
-
-/** Offset 0x00C7 - Scrambler Support
- This option enables data scrambling in memory.
- $EN_DIS
-**/
- UINT8 ScramblerSupport;
-
-/** Offset 0x00C8 - Skip Multi-Processor Initialization
- When this is skipped, boot loader must initialize processors before SilicionInit
- API. </b>0: Initialize; <b>1: Skip
- $EN_DIS
-**/
- UINT8 SkipMpInit;
-
-/** Offset 0x00C9
-**/
- UINT8 UnusedUpdSpace1[15];
-
-/** Offset 0x00D8 - SPD Profile Selected
- Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
- Profile 1, 3=XMP Profile 2
- 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
-**/
- UINT8 SpdProfileSelected;
-
-/** Offset 0x00D9 - Memory Reference Clock
- 100MHz, 133MHz.
- 0:133MHz, 1:100MHz
-**/
- UINT8 RefClk;
-
-/** Offset 0x00DA - Memory Voltage
- Memory Voltage Override (Vddq). Default = no override
- 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
- Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
-**/
- UINT16 VddVoltage;
-
-/** Offset 0x00DC - Memory Ratio
- Automatic or the frequency will equal ratio times reference clock. Set to Auto to
- recalculate memory timings listed below.
- 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
-**/
- UINT8 Ratio;
-
-/** Offset 0x00DD - QCLK Odd Ratio
- Adds 133 or 100 MHz to QCLK frequency, depending on RefClk
- $EN_DIS
-**/
- UINT8 OddRatioMode;
-
-/** Offset 0x00DE - tCL
- CAS Latency, 0: AUTO, max: 31
-**/
- UINT8 tCL;
-
-/** Offset 0x00DF - tCWL
- Min CAS Write Latency Delay Time, 0: AUTO, max: 34
-**/
- UINT8 tCWL;
-
-/** Offset 0x00E0 - tRCD/tRP
- RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
-**/
- UINT8 tRCDtRP;
-
-/** Offset 0x00E1 - tRRD
- Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
-**/
- UINT8 tRRD;
-
-/** Offset 0x00E2 - tFAW
- Min Four Activate Window Delay Time, 0: AUTO, max: 63
-**/
- UINT16 tFAW;
-
-/** Offset 0x00E4 - tRAS
- RAS Active Time, 0: AUTO, max: 64
-**/
- UINT16 tRAS;
-
-/** Offset 0x00E6 - tREFI
- Refresh Interval, 0: AUTO, max: 65535
-**/
- UINT16 tREFI;
-
-/** Offset 0x00E8 - tRFC
- Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
-**/
- UINT16 tRFC;
-
-/** Offset 0x00EA - tRTP
- Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
- values: 5, 6, 7, 8, 9, 10, 12
-**/
- UINT8 tRTP;
-
-/** Offset 0x00EB - tWR
- Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
- 20, 24, 30, 34, 40
- 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
- 34:34, 40:40
-**/
- UINT8 tWR;
-
-/** Offset 0x00EC - tWTR
- Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
-**/
- UINT8 tWTR;
-
-/** Offset 0x00ED - NMode
- System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
-**/
- UINT8 NModeSupport;
-
-/** Offset 0x00EE - DllBwEn[0]
- DllBwEn[0], for 1067 (0..7)
-**/
- UINT8 DllBwEn0;
-
-/** Offset 0x00EF - DllBwEn[1]
- DllBwEn[1], for 1333 (0..7)
-**/
- UINT8 DllBwEn1;
-
-/** Offset 0x00F0 - DllBwEn[2]
- DllBwEn[2], for 1600 (0..7)
-**/
- UINT8 DllBwEn2;
-
-/** Offset 0x00F1 - DllBwEn[3]
- DllBwEn[3], for 1867 and up (0..7)
-**/
- UINT8 DllBwEn3;
-
-/** Offset 0x00F2 - ISVT IO Port Address
- ISVT IO Port Address. 0=Minimal, 0xFF=Maximum, 0x99=Default
-**/
- UINT8 IsvtIoPort;
-
-/** Offset 0x00F3 - CPU Trace Hub Mode
- Select 'Target Debugger' if Trace Hub is used by target debugger software or 'Disable'
- trace hub functionality.
- 0: Disable, 1:Target Debugger Mode
-**/
- UINT8 CpuTraceHubMode;
-
-/** Offset 0x00F4 - CPU Trace Hub Memory Region 0
- CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
- 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
- 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
-**/
- UINT8 CpuTraceHubMemReg0Size;
-
-/** Offset 0x00F5 - CPU Trace Hub Memory Region 1
- CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
- 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
- 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
-**/
- UINT8 CpuTraceHubMemReg1Size;
-
-/** Offset 0x00F6 - Enable or Disable Peci C10 Reset command
- Enable or Disable Peci C10 Reset command. If Enabled, BIOS will send the CPU message
- to disable peci reset on C10 exit. The default value is <b>0: Disable</b> for CNL,
- and <b>1: Enable</b> for all other CPU's
- $EN_DIS
-**/
- UINT8 PeciC10Reset;
-
-/** Offset 0x00F7 - Enable or Disable Peci Sx Reset command
- Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
- $EN_DIS
-**/
- UINT8 PeciSxReset;
-
-/** Offset 0x00F8
-**/
- UINT8 UnusedUpdSpace2[4];
-
-/** Offset 0x00FC - Enable Intel HD Audio (Azalia)
- 0: Disable, 1: Enable (Default) Azalia controller
- $EN_DIS
-**/
- UINT8 PchHdaEnable;
-
-/** Offset 0x00FD - Enable PCH ISH Controller
- 0: Disable, 1: Enable (Default) ISH Controller
- $EN_DIS
-**/
- UINT8 PchIshEnable;
-
-/** Offset 0x00FE - HECI Timeouts
- 0: Disable, 1: Enable (Default) timeout check for HECI
- $EN_DIS
-**/
- UINT8 HeciTimeouts;
-
-/** Offset 0x00FF
-**/
- UINT8 UnusedUpdSpace3;
-
-/** Offset 0x0100 - HECI1 BAR address
- BAR address of HECI1
-**/
- UINT32 Heci1BarAddress;
-
-/** Offset 0x0104 - HECI2 BAR address
- BAR address of HECI2
-**/
- UINT32 Heci2BarAddress;
-
-/** Offset 0x0108 - HECI3 BAR address
- BAR address of HECI3
-**/
- UINT32 Heci3BarAddress;
-
-/** Offset 0x010C - SG dGPU Power Delay
- SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
- 300=300 microseconds
-**/
- UINT16 SgDelayAfterPwrEn;
-
-/** Offset 0x010E - SG dGPU Reset Delay
- SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
- microseconds
-**/
- UINT16 SgDelayAfterHoldReset;
-
-/** Offset 0x0110 - MMIO size adjustment for AUTO mode
- Positive number means increasing MMIO size, Negative value means decreasing MMIO
- size: 0 (Default)=no change to AUTO mode MMIO size
-**/
- UINT16 MmioSizeAdjustment;
-
-/** Offset 0x0112 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
- Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
- Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
- $EN_DIS
-**/
- UINT8 DmiGen3ProgramStaticEq;
-
-/** Offset 0x0113 - Enable/Disable PEG 0
- Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
- it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
- 0:Disable, 1:Enable, 2:AUTO
-**/
- UINT8 Peg0Enable;
-
-/** Offset 0x0114 - Enable/Disable PEG 1
- Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
- it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
- 0:Disable, 1:Enable, 2:AUTO
-**/
- UINT8 Peg1Enable;
-
-/** Offset 0x0115 - Enable/Disable PEG 2
- Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
- it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
- 0:Disable, 1:Enable, 2:AUTO
-**/
- UINT8 Peg2Enable;
-
-/** Offset 0x0116 - Enable/Disable PEG 3
- Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
- it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
- 0:Disable, 1:Enable, 2:AUTO
-**/
- UINT8 Peg3Enable;
-
-/** Offset 0x0117 - PEG 0 Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 Peg0MaxLinkSpeed;
-
-/** Offset 0x0118 - PEG 1 Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 Peg1MaxLinkSpeed;
-
-/** Offset 0x0119 - PEG 2 Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 Peg2MaxLinkSpeed;
-
-/** Offset 0x011A - PEG 3 Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 Peg3MaxLinkSpeed;
-
-/** Offset 0x011B - PEG 0 Max Link Width
- Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
- Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8
- 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8
-**/
- UINT8 Peg0MaxLinkWidth;
-
-/** Offset 0x011C - PEG 1 Max Link Width
- Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
- Limit Link to x2, (0x3):Limit Link to x4
- 0:Auto, 1:x1, 2:x2, 3:x4
-**/
- UINT8 Peg1MaxLinkWidth;
-
-/** Offset 0x011D - PEG 2 Max Link Width
- Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
- Limit Link to x2
- 0:Auto, 1:x1, 2:x2
-**/
- UINT8 Peg2MaxLinkWidth;
-
-/** Offset 0x011E - PEG 3 Max Link Width
- Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
- Limit Link to x2
- 0:Auto, 1:x1, 2:x2
-**/
- UINT8 Peg3MaxLinkWidth;
-
-/** Offset 0x011F - Power down unused lanes on PEG 0
- (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
- on the max possible link width
- 0:No power saving, 1:Auto
-**/
- UINT8 Peg0PowerDownUnusedLanes;
-
-/** Offset 0x0120 - Power down unused lanes on PEG 1
- (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
- on the max possible link width
- 0:No power saving, 1:Auto
-**/
- UINT8 Peg1PowerDownUnusedLanes;
-
-/** Offset 0x0121 - Power down unused lanes on PEG 2
- (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
- on the max possible link width
- 0:No power saving, 1:Auto
-**/
- UINT8 Peg2PowerDownUnusedLanes;
-
-/** Offset 0x0122 - Power down unused lanes on PEG 3
- (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
- on the max possible link width
- 0:No power saving, 1:Auto
-**/
- UINT8 Peg3PowerDownUnusedLanes;
-
-/** Offset 0x0123 - PCIe ASPM programming will happen in relation to the Oprom
- Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
- Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
- Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
- 0:Before, 1:After
-**/
- UINT8 InitPcieAspmAfterOprom;
-
-/** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking
- PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,
- Disable SSC(0X1) - Disable SSC per platform design or for compliance testing
- 0:Normal Operation, 1:Disable SSC
-**/
- UINT8 PegDisableSpreadSpectrumClocking;
-
-/** Offset 0x0125
-**/
- UINT8 UnusedUpdSpace4[3];
-
-/** Offset 0x0128 - DMI Gen3 Root port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
-**/
- UINT8 DmiGen3RootPortPreset[8];
-
-/** Offset 0x0130 - DMI Gen3 End port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
-**/
- UINT8 DmiGen3EndPointPreset[8];
-
-/** Offset 0x0138 - DMI Gen3 End port Hint values per lane
- Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
-**/
- UINT8 DmiGen3EndPointHint[8];
-
-/** Offset 0x0140 - DMI Gen3 RxCTLEp per-Bundle control
- Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
-**/
- UINT8 DmiGen3RxCtlePeaking[4];
-
-/** Offset 0x0144 - Thermal Velocity Boost Ratio clipping
- 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction
- caused by high package temperatures for processors that implement the Intel Thermal
- Velocity Boost (TVB) feature
- 0: Disabled, 1: Enabled
-**/
- UINT8 TvbRatioClipping;
-
-/** Offset 0x0145 - Thermal Velocity Boost voltage optimization
- 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
- for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
- 0: Disabled, 1: Enabled
-**/
- UINT8 TvbVoltageOptimization;
-
-/** Offset 0x0146
-**/
- UINT8 UnusedUpdSpace5[2];
-
-/** Offset 0x0148 - PEG Gen3 RxCTLEp per-Bundle control
- Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
-**/
- UINT8 PegGen3RxCtlePeaking[10];
-
-/** Offset 0x0152 - Memory data pointer for saved preset search results
- The reference code will store the Gen3 Preset Search results in the SaDataHob's
- PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
- skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
-**/
- UINT32 PegDataPtr;
-
-/** Offset 0x0156 - PEG PERST# GPIO information
- The reference code will use the information in this structure in order to reset
- PCIe Gen3 devices during equalization, if necessary
-**/
- UINT8 PegGpioData[28];
-
-/** Offset 0x0172 - PCIe Hot Plug Enable/Disable per port
- 0(Default): Disable, 1: Enable
-**/
- UINT8 PegRootPortHPE[4];
-
-/** Offset 0x0176 - DeEmphasis control for DMI
- DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
- 0: -6dB, 1: -3.5dB
-**/
- UINT8 DmiDeEmphasis;
-
-/** Offset 0x0177 - Selection of the primary display device
- 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
- 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
-**/
- UINT8 PrimaryDisplay;
-
-/** Offset 0x0178 - Selection of iGFX GTT Memory size
- 1=2MB, 2=4MB, 3=8MB, Default is 3
- 1:2MB, 2:4MB, 3:8MB
-**/
- UINT16 GttSize;
-
-/** Offset 0x017A - Temporary MMIO address for GMADR
- The reference code will use this as Temporary MMIO address space to access GMADR
- Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
- (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress
- - 0x1) (Where ApertureSize = 256MB)
-**/
- UINT32 GmAdr;
-
-/** Offset 0x017E - Temporary MMIO address for GTTMMADR
- The reference code will use this as Temporary MMIO address space to access GTTMMADR
- Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
- to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
- + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
-**/
- UINT32 GttMmAdr;
-
-/** Offset 0x0182 - Selection of PSMI Region size
- 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
- 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
-**/
- UINT8 PsmiRegionSize;
-
-/** Offset 0x0183 - Switchable Graphics GPIO information for PEG 0
- Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
-**/
- UINT8 SaRtd3Pcie0Gpio[24];
-
-/** Offset 0x019B - Switchable Graphics GPIO information for PEG 1
- Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
-**/
- UINT8 SaRtd3Pcie1Gpio[24];
-
-/** Offset 0x01B3 - Switchable Graphics GPIO information for PEG 2
- Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
-**/
- UINT8 SaRtd3Pcie2Gpio[24];
-
-/** Offset 0x01CB - Switchable Graphics GPIO information for PEG 3
- Switchable Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs
-**/
- UINT8 SaRtd3Pcie3Gpio[24];
-
-/** Offset 0x01E3 - Enable/Disable MRC TXT dependency
- When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
- MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
- $EN_DIS
-**/
- UINT8 TxtImplemented;
-
-/** Offset 0x01E4 - Enable/Disable SA OcSupport
- Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
- $EN_DIS
-**/
- UINT8 SaOcSupport;
-
-/** Offset 0x01E5 - GT slice Voltage Mode
- 0(Default): Adaptive, 1: Override
- 0: Adaptive, 1: Override
-**/
- UINT8 GtVoltageMode;
-
-/** Offset 0x01E6 - Maximum GTs turbo ratio override
- 0(Default)=Minimal/Auto, 60=Maximum
-**/
- UINT8 GtMaxOcRatio;
-
-/** Offset 0x01E7 - The voltage offset applied to GT slice
- 0(Default)=Minimal, 1000=Maximum
-**/
- UINT16 GtVoltageOffset;
-
-/** Offset 0x01E9 - The GT slice voltage override which is applied to the entire range of GT frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtVoltageOverride;
-
-/** Offset 0x01EB - adaptive voltage applied during turbo frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtExtraTurboVoltage;
-
-/** Offset 0x01ED - voltage offset applied to the SA
- 0(Default)=Minimal, 1000=Maximum
-**/
- UINT16 SaVoltageOffset;
-
-/** Offset 0x01EF - PCIe root port Function number for Switchable Graphics dGPU
- Root port Index number to indicate which PCIe root port has dGPU
-**/
- UINT8 RootPortIndex;
-
-/** Offset 0x01F0 - Realtime Memory Timing
- 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
- realtime memory timing changes after MRC_DONE.
- 0: Disabled, 1: Enabled
-**/
- UINT8 RealtimeMemoryTiming;
-
-/** Offset 0x01F1 - Enable/Disable SA IPU
- Enable(Default): Enable SA IPU, Disable: Disable SA IPU
- $EN_DIS
-**/
- UINT8 SaIpuEnable;
-
-/** Offset 0x01F2 - IPU IMR Configuration
- 0:IPU Camera, 1:IPU Gen Default is 0
- 0:IPU Camera, 1:IPU Gen
-**/
- UINT8 SaIpuImrConfiguration;
-
-/** Offset 0x01F3 - Selection of PSMI Support On/Off
- 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
- $EN_DIS
-**/
- UINT8 GtPsmiSupport;
-
-/** Offset 0x01F4 - GT unslice Voltage Mode
- 0(Default): Adaptive, 1: Override
- 0: Adaptive, 1: Override
-**/
- UINT8 GtusVoltageMode;
-
-/** Offset 0x01F5 - voltage offset applied to GT unslice
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtusVoltageOffset;
-
-/** Offset 0x01F7 - GT unslice voltage override which is applied to the entire range of GT frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtusVoltageOverride;
-
-/** Offset 0x01F9 - adaptive voltage applied during turbo frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtusExtraTurboVoltage;
-
-/** Offset 0x01FB - Maximum GTus turbo ratio override
- 0(Default)=Minimal, 60=Maximum
-**/
- UINT8 GtusMaxOcRatio;
-
-/** Offset 0x01FC - SaPreMemProductionRsvd
- Reserved for SA Pre-Mem Production
- $EN_DIS
-**/
- UINT8 SaPreMemProductionRsvd[4];
-
-/** Offset 0x0200 - BIST on Reset
- Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 BistOnReset;
-
-/** Offset 0x0201 - Skip Stop PBET Timer Enable/Disable
- Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 SkipStopPbet;
-
-/** Offset 0x0202 - C6DRAM power gating feature
- This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
- power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
- feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
- $EN_DIS
-**/
- UINT8 EnableC6Dram;
-
-/** Offset 0x0203 - Over clocking support
- Over clocking support; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 OcSupport;
-
-/** Offset 0x0204 - Over clocking Lock
- Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 OcLock;
-
-/** Offset 0x0205 - Maximum Core Turbo Ratio Override
- Maximum core turbo ratio override allows to increase CPU core frequency beyond the
- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
-**/
- UINT8 CoreMaxOcRatio;
-
-/** Offset 0x0206 - Core voltage mode
- Core voltage mode; <b>0: Adaptive</b>; 1: Override.
- $EN_DIS
-**/
- UINT8 CoreVoltageMode;
-
-/** Offset 0x0207 - Program Cache Attributes
- Program Cache Attributes; <b>0: Program</b>; 1: Disable Program.
- $EN_DIS
-**/
- UINT8 DisableMtrrProgram;
-
-/** Offset 0x0208 - Maximum clr turbo ratio override
- Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-255
-**/
- UINT8 RingMaxOcRatio;
-
-/** Offset 0x0209 - Hyper Threading Enable/Disable
- Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 HyperThreading;
-
-/** Offset 0x020A - CPU ratio value
- CPU ratio value. Valid Range 0 to 63. CPU Ratio is 0 when disabled.
-**/
- UINT8 CpuRatio;
-
-/** Offset 0x020B - Boot frequency
- Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
- <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
- is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
- 0:0, 1:1, 2:2
-**/
- UINT8 BootFrequency;
-
-/** Offset 0x020C - Number of active cores
- Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
- 2 </b>;<b>3: 3 </b>
- 0:All, 1:1, 2:2, 3:3
-**/
- UINT8 ActiveCoreCount;
-
-/** Offset 0x020D - Processor Early Power On Configuration FCLK setting
- <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
- 2: 400 MHz. - 3: Reserved
- 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
-**/
- UINT8 FClkFrequency;
-
-/** Offset 0x020E - Set JTAG power in C10 and deeper power states
- False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
- and deeper power states for debug purpose. <b>0: False</b>; 1: True.
- 0: False, 1: True
-**/
- UINT8 JtagC10PowerGateDisable;
-
-/** Offset 0x020F - Enable or Disable VMX
- Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 VmxEnable;
-
-/** Offset 0x0210 - AVX2 Ratio Offset
- 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
- vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
-**/
- UINT8 Avx2RatioOffset;
-
-/** Offset 0x0211 - AVX3 Ratio Offset
- 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
- vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
-**/
- UINT8 Avx3RatioOffset;
-
-/** Offset 0x0212 - BCLK Adaptive Voltage Enable
- When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
- Disable;<b> 1: Enable
- $EN_DIS
-**/
- UINT8 BclkAdaptiveVoltage;
-
-/** Offset 0x0213 - Core PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 CorePllVoltageOffset;
-
-/** Offset 0x0214 - core voltage override
- The core voltage override which is applied to the entire range of cpu core frequencies.
- Valid Range 0 to 2000
-**/
- UINT16 CoreVoltageOverride;
-
-/** Offset 0x0216 - Core Turbo voltage Adaptive
- Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
- Valid Range 0 to 2000
-**/
- UINT16 CoreVoltageAdaptive;
-
-/** Offset 0x0218 - Core Turbo voltage Offset
- The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
-**/
- UINT16 CoreVoltageOffset;
-
-/** Offset 0x021A - Ring Downbin
- Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
- lower than the core ratio.0: Disable; <b>1: Enable.</b>
- $EN_DIS
-**/
- UINT8 RingDownBin;
-
-/** Offset 0x021B - Ring voltage mode
- Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
- $EN_DIS
-**/
- UINT8 RingVoltageMode;
-
-/** Offset 0x021C - Ring voltage override
- The ring voltage override which is applied to the entire range of cpu ring frequencies.
- Valid Range 0 to 2000
-**/
- UINT16 RingVoltageOverride;
-
-/** Offset 0x021E - Ring Turbo voltage Adaptive
- Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
- Valid Range 0 to 2000
-**/
- UINT16 RingVoltageAdaptive;
-
-/** Offset 0x0220 - Ring Turbo voltage Offset
- The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
-**/
- UINT16 RingVoltageOffset;
-
-/** Offset 0x0222 - TjMax Offset
- TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
- TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
-**/
- UINT8 TjMaxOffset;
-
-/** Offset 0x0223 - BiosGuard
- Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
- $EN_DIS
-**/
- UINT8 BiosGuard;
-
-/** Offset 0x0224
-**/
- UINT8 BiosGuardToolsInterface;
-
-/** Offset 0x0225 - EnableSgx
- Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
- 0: Disable, 1: Enable, 2: Software Control
-**/
- UINT8 EnableSgx;
-
-/** Offset 0x0226 - Txt
- Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
- $EN_DIS
-**/
- UINT8 Txt;
-
-/** Offset 0x0227
-**/
- UINT8 UnusedUpdSpace6;
-
-/** Offset 0x0228 - PrmrrSize
- 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000
-**/
- UINT32 PrmrrSize;
-
-/** Offset 0x022C - SinitMemorySize
- Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
-**/
- UINT32 SinitMemorySize;
-
-/** Offset 0x0230 - TxtHeapMemorySize
- Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
-**/
- UINT32 TxtHeapMemorySize;
-
-/** Offset 0x0234 - TxtDprMemorySize
- Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
-**/
- UINT32 TxtDprMemorySize;
-
-/** Offset 0x0238 - TxtDprMemoryBase
- Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
-**/
- UINT64 TxtDprMemoryBase;
-
-/** Offset 0x0240 - BiosAcmBase
- Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
-**/
- UINT32 BiosAcmBase;
-
-/** Offset 0x0244 - BiosAcmSize
- Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
-**/
- UINT32 BiosAcmSize;
-
-/** Offset 0x0248 - ApStartupBase
- Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
-**/
- UINT32 ApStartupBase;
-
-/** Offset 0x024C - TgaSize
- Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
-**/
- UINT32 TgaSize;
-
-/** Offset 0x0250 - TxtLcpPdBase
- Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
-**/
- UINT64 TxtLcpPdBase;
-
-/** Offset 0x0258 - TxtLcpPdSize
- Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
-**/
- UINT64 TxtLcpPdSize;
-
-/** Offset 0x0260 - IsTPMPresence
- IsTPMPresence default values
-**/
- UINT8 IsTPMPresence;
-
-/** Offset 0x0261 - ReservedSecurityPreMem
- Reserved for Security Pre-Mem
- $EN_DIS
-**/
- UINT8 ReservedSecurityPreMem[15];
-
-/** Offset 0x0270 - Enable PCH HSIO PCIE Rx Set Ctle
- Enable PCH PCIe Gen 3 Set CTLE Value.
-**/
- UINT8 PchPcieHsioRxSetCtleEnable[24];
-
-/** Offset 0x0288 - PCH HSIO PCIE Rx Set Ctle Value
- PCH PCIe Gen 3 Set CTLE Value.
-**/
- UINT8 PchPcieHsioRxSetCtle[24];
-
-/** Offset 0x02A0 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
-
-/** Offset 0x02B8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
-
-/** Offset 0x02D0 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
-
-/** Offset 0x02E8 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
-
-/** Offset 0x0300 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
-
-/** Offset 0x0318 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
-
-/** Offset 0x0330 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
-
-/** Offset 0x0348 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
- PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen1DeEmph[24];
-
-/** Offset 0x0360 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
-
-/** Offset 0x0378 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
- PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
-
-/** Offset 0x0390 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
-
-/** Offset 0x03A8 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
- PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
-
-/** Offset 0x03C0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
-
-/** Offset 0x03C8 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen1EqBoostMag[8];
-
-/** Offset 0x03D0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
-
-/** Offset 0x03D8 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen2EqBoostMag[8];
-
-/** Offset 0x03E0 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
-
-/** Offset 0x03E8 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen3EqBoostMag[8];
-
-/** Offset 0x03F0 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
-
-/** Offset 0x03F8 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen1DownscaleAmp[8];
-
-/** Offset 0x0400 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
-
-/** Offset 0x0408 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen2DownscaleAmp[8];
-
-/** Offset 0x0410 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
-
-/** Offset 0x0418 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen3DownscaleAmp[8];
-
-/** Offset 0x0420 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen1DeEmphEnable[8];
-
-/** Offset 0x0428 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen1DeEmph[8];
-
-/** Offset 0x0430 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen2DeEmphEnable[8];
-
-/** Offset 0x0438 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen2DeEmph[8];
-
-/** Offset 0x0440 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen3DeEmphEnable[8];
-
-/** Offset 0x0448 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen3DeEmph[8];
-
-/** Offset 0x0450 - PCH LPC Enhance the port 8xh decoding
- Original LPC only decodes one byte of port 80h.
- $EN_DIS
-**/
- UINT8 PchLpcEnhancePort8xhDecoding;
-
-/** Offset 0x0451 - PCH Port80 Route
- Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
- $EN_DIS
-**/
- UINT8 PchPort80Route;
-
-/** Offset 0x0452 - Enable SMBus ARP support
- Enable SMBus ARP support.
- $EN_DIS
-**/
- UINT8 SmbusArpEnable;
-
-/** Offset 0x0453 - Number of RsvdSmbusAddressTable.
- The number of elements in the RsvdSmbusAddressTable.
-**/
- UINT8 PchNumRsvdSmbusAddresses;
-
-/** Offset 0x0454 - SMBUS Base Address
- SMBUS Base Address (IO space).
-**/
- UINT16 PchSmbusIoBase;
-
-/** Offset 0x0456 - Size of PCIe IMR.
- Size of PCIe IMR in megabytes
-**/
- UINT16 PcieImrSize;
-
-/** Offset 0x0458 - Point of RsvdSmbusAddressTable
- Array of addresses reserved for non-ARP-capable SMBus devices.
-**/
- UINT32 RsvdSmbusAddressTablePtr;
-
-/** Offset 0x045C - Enable PCIE RP Mask
- Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
- for port1, bit1 for port2, and so on.
-**/
- UINT32 PcieRpEnableMask;
-
-/** Offset 0x0460 - Enable PCIe IMR
- 0:Disable, 1:Enable
- $EN_DIS
-**/
- UINT8 PcieImrEnabled;
-
-/** Offset 0x0461 - Root port number for IMR.
- Root port number for IMR.
-**/
- UINT8 ImrRpSelection;
-
-/** Offset 0x0462 - Enable SMBus Alert Pin
- Enable SMBus Alert Pin.
- $EN_DIS
-**/
- UINT8 PchSmbAlertEnable;
-
-/** Offset 0x0463 - ReservedPchPreMem
- Reserved for Pch Pre-Mem
- $EN_DIS
-**/
- UINT8 ReservedPchPreMem[13];
-
-/** Offset 0x0470 - Debug Interfaces
- Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
- BIT2 - Not used.
-**/
- UINT8 PcdDebugInterfaceFlags;
-
-/** Offset 0x0471 - PcdSerialIoUartNumber
- Select SerialIo Uart Controller for debug.
- 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
- UINT8 PcdSerialIoUartNumber;
-
-/** Offset 0x0472 - ISA Serial Base selection
- Select ISA Serial Base address. Default is 0x3F8.
- 0:0x3F8, 1:0x2F8
-**/
- UINT8 PcdIsaSerialUartBase;
-
-/** Offset 0x0473 - GT PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 GtPllVoltageOffset;
-
-/** Offset 0x0474 - Ring PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 RingPllVoltageOffset;
-
-/** Offset 0x0475 - System Agent PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 SaPllVoltageOffset;
-
-/** Offset 0x0476 - Memory Controller PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 McPllVoltageOffset;
-
-/** Offset 0x0477 - MRC Safe Config
- Enables/Disable MRC Safe Config
- $EN_DIS
-**/
- UINT8 MrcSafeConfig;
-
-/** Offset 0x0478 - PcdSerialDebugBaudRate
- Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
- 3:9600, 4:19200, 6:56700, 7:115200
-**/
- UINT8 PcdSerialDebugBaudRate;
-
-/** Offset 0x0479 - HobBufferSize
- Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
- total HOB size).
- 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
-**/
- UINT8 HobBufferSize;
-
-/** Offset 0x047A - Early Command Training
- Enables/Disable Early Command Training
- $EN_DIS
-**/
- UINT8 ECT;
-
-/** Offset 0x047B - SenseAmp Offset Training
- Enables/Disable SenseAmp Offset Training
- $EN_DIS
-**/
- UINT8 SOT;
-
-/** Offset 0x047C - Early ReadMPR Timing Centering 2D
- Enables/Disable Early ReadMPR Timing Centering 2D
- $EN_DIS
-**/
- UINT8 ERDMPRTC2D;
-
-/** Offset 0x047D - Read MPR Training
- Enables/Disable Read MPR Training
- $EN_DIS
-**/
- UINT8 RDMPRT;
-
-/** Offset 0x047E - Receive Enable Training
- Enables/Disable Receive Enable Training
- $EN_DIS
-**/
- UINT8 RCVET;
-
-/** Offset 0x047F - Jedec Write Leveling
- Enables/Disable Jedec Write Leveling
- $EN_DIS
-**/
- UINT8 JWRL;
-
-/** Offset 0x0480 - Early Write Time Centering 2D
- Enables/Disable Early Write Time Centering 2D
- $EN_DIS
-**/
- UINT8 EWRTC2D;
-
-/** Offset 0x0481 - Early Read Time Centering 2D
- Enables/Disable Early Read Time Centering 2D
- $EN_DIS
-**/
- UINT8 ERDTC2D;
-
-/** Offset 0x0482 - Write Timing Centering 1D
- Enables/Disable Write Timing Centering 1D
- $EN_DIS
-**/
- UINT8 WRTC1D;
-
-/** Offset 0x0483 - Write Voltage Centering 1D
- Enables/Disable Write Voltage Centering 1D
- $EN_DIS
-**/
- UINT8 WRVC1D;
-
-/** Offset 0x0484 - Read Timing Centering 1D
- Enables/Disable Read Timing Centering 1D
- $EN_DIS
-**/
- UINT8 RDTC1D;
-
-/** Offset 0x0485 - Dimm ODT Training
- Enables/Disable Dimm ODT Training
- $EN_DIS
-**/
- UINT8 DIMMODTT;
-
-/** Offset 0x0486 - DIMM RON Training
- Enables/Disable DIMM RON Training
- $EN_DIS
-**/
- UINT8 DIMMRONT;
-
-/** Offset 0x0487 - Write Drive Strength/Equalization 2D
- Enables/Disable Write Drive Strength/Equalization 2D
- $EN_DIS
-**/
- UINT8 WRDSEQT;
-
-/** Offset 0x0488 - Write Slew Rate Training
- Enables/Disable Write Slew Rate Training
- $EN_DIS
-**/
- UINT8 WRSRT;
-
-/** Offset 0x0489 - Read ODT Training
- Enables/Disable Read ODT Training
- $EN_DIS
-**/
- UINT8 RDODTT;
-
-/** Offset 0x048A - Read Equalization Training
- Enables/Disable Read Equalization Training
- $EN_DIS
-**/
- UINT8 RDEQT;
-
-/** Offset 0x048B - Read Amplifier Training
- Enables/Disable Read Amplifier Training
- $EN_DIS
-**/
- UINT8 RDAPT;
-
-/** Offset 0x048C - Write Timing Centering 2D
- Enables/Disable Write Timing Centering 2D
- $EN_DIS
-**/
- UINT8 WRTC2D;
-
-/** Offset 0x048D - Read Timing Centering 2D
- Enables/Disable Read Timing Centering 2D
- $EN_DIS
-**/
- UINT8 RDTC2D;
-
-/** Offset 0x048E - Write Voltage Centering 2D
- Enables/Disable Write Voltage Centering 2D
- $EN_DIS
-**/
- UINT8 WRVC2D;
-
-/** Offset 0x048F - Read Voltage Centering 2D
- Enables/Disable Read Voltage Centering 2D
- $EN_DIS
-**/
- UINT8 RDVC2D;
-
-/** Offset 0x0490 - Command Voltage Centering
- Enables/Disable Command Voltage Centering
- $EN_DIS
-**/
- UINT8 CMDVC;
-
-/** Offset 0x0491 - Late Command Training
- Enables/Disable Late Command Training
- $EN_DIS
-**/
- UINT8 LCT;
-
-/** Offset 0x0492 - Round Trip Latency Training
- Enables/Disable Round Trip Latency Training
- $EN_DIS
-**/
- UINT8 RTL;
-
-/** Offset 0x0493 - Turn Around Timing Training
- Enables/Disable Turn Around Timing Training
- $EN_DIS
-**/
- UINT8 TAT;
-
-/** Offset 0x0494 - Memory Test
- Enables/Disable Memory Test
- $EN_DIS
-**/
- UINT8 MEMTST;
-
-/** Offset 0x0495 - DIMM SPD Alias Test
- Enables/Disable DIMM SPD Alias Test
- $EN_DIS
-**/
- UINT8 ALIASCHK;
-
-/** Offset 0x0496 - Receive Enable Centering 1D
- Enables/Disable Receive Enable Centering 1D
- $EN_DIS
-**/
- UINT8 RCVENC1D;
-
-/** Offset 0x0497 - Retrain Margin Check
- Enables/Disable Retrain Margin Check
- $EN_DIS
-**/
- UINT8 RMC;
-
-/** Offset 0x0498 - Write Drive Strength Up/Dn independently
- Enables/Disable Write Drive Strength Up/Dn independently
- $EN_DIS
-**/
- UINT8 WRDSUDT;
-
-/** Offset 0x0499 - ECC Support
- Enables/Disable ECC Support
- $EN_DIS
-**/
- UINT8 EccSupport;
-
-/** Offset 0x049A - Memory Remap
- Enables/Disable Memory Remap
- $EN_DIS
-**/
- UINT8 RemapEnable;
-
-/** Offset 0x049B - Rank Interleave support
- Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
- the same time.
- $EN_DIS
-**/
- UINT8 RankInterleave;
-
-/** Offset 0x049C - Enhanced Interleave support
- Enables/Disable Enhanced Interleave support
- $EN_DIS
-**/
- UINT8 EnhancedInterleave;
-
-/** Offset 0x049D - Memory Trace
- Enable Memory Trace of Ch 0 to Ch 1 using Stacked Mode. Both channels must be of
- equal size. This option may change TOLUD and REMAP values as needed.
- $EN_DIS
-**/
- UINT8 MemoryTrace;
-
-/** Offset 0x049E - Ch Hash Support
- Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
- $EN_DIS
-**/
- UINT8 ChHashEnable;
-
-/** Offset 0x049F - Extern Therm Status
- Enables/Disable Extern Therm Status
- $EN_DIS
-**/
- UINT8 EnableExtts;
-
-/** Offset 0x04A0 - Closed Loop Therm Manage
- Enables/Disable Closed Loop Therm Manage
- $EN_DIS
-**/
- UINT8 EnableCltm;
-
-/** Offset 0x04A1 - Open Loop Therm Manage
- Enables/Disable Open Loop Therm Manage
- $EN_DIS
-**/
- UINT8 EnableOltm;
-
-/** Offset 0x04A2 - DDR PowerDown and idle counter
- Enables/Disable DDR PowerDown and idle counter
- $EN_DIS
-**/
- UINT8 EnablePwrDn;
-
-/** Offset 0x04A3 - DDR PowerDown and idle counter - LPDDR
- Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
- $EN_DIS
-**/
- UINT8 EnablePwrDnLpddr;
-
-/** Offset 0x04A4 - Use user provided power weights, scale factor, and channel power floor values
- Enables/Disable Use user provided power weights, scale factor, and channel power
- floor values
- $EN_DIS
-**/
- UINT8 UserPowerWeightsEn;
-
-/** Offset 0x04A5 - RAPL PL Lock
- Enables/Disable RAPL PL Lock
- $EN_DIS
-**/
- UINT8 RaplLim2Lock;
-
-/** Offset 0x04A6 - RAPL PL 2 enable
- Enables/Disable RAPL PL 2 enable
- $EN_DIS
-**/
- UINT8 RaplLim2Ena;
-
-/** Offset 0x04A7 - RAPL PL 1 enable
- Enables/Disable RAPL PL 1 enable
- $EN_DIS
-**/
- UINT8 RaplLim1Ena;
-
-/** Offset 0x04A8 - SelfRefresh Enable
- Enables/Disable SelfRefresh Enable
- $EN_DIS
-**/
- UINT8 SrefCfgEna;
-
-/** Offset 0x04A9 - Throttler CKEMin Defeature - LPDDR
- Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
- $EN_DIS
-**/
- UINT8 ThrtCkeMinDefeatLpddr;
-
-/** Offset 0x04AA - Throttler CKEMin Defeature
- Enables/Disable Throttler CKEMin Defeature
- $EN_DIS
-**/
- UINT8 ThrtCkeMinDefeat;
-
-/** Offset 0x04AB - Enable RH Prevention
- Enables/Disable RH Prevention
- $EN_DIS
-**/
- UINT8 RhPrevention;
-
-/** Offset 0x04AC - Exit On Failure (MRC)
- Enables/Disable Exit On Failure (MRC)
- $EN_DIS
-**/
- UINT8 ExitOnFailure;
-
-/** Offset 0x04AD - LPDDR Thermal Sensor
- Enables/Disable LPDDR Thermal Sensor
- $EN_DIS
-**/
- UINT8 DdrThermalSensor;
-
-/** Offset 0x04AE - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
- Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
- $EN_DIS
-**/
- UINT8 Ddr4DdpSharedClock;
-
-/** Offset 0x04AF - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
- ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
- $EN_DIS
-**/
- UINT8 Ddr4DdpSharedZq;
-
-/** Offset 0x04B0 - Ch Hash Mask
- Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
- BITS [19:6
-**/
- UINT16 ChHashMask;
-
-/** Offset 0x04B2 - Base reference clock value
- Base reference clock value, in Hertz(Default is 125Hz)
- 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
-**/
- UINT32 BClkFrequency;
-
-/** Offset 0x04B6 - Ch Hash Interleaved Bit
- Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
- the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
- 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
-**/
- UINT8 ChHashInterleaveBit;
-
-/** Offset 0x04B7 - Energy Scale Factor
- Energy Scale Factor, Default is 4
-**/
- UINT8 EnergyScaleFact;
-
-/** Offset 0x04B8 - EPG DIMM Idd3N
- Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
- a per DIMM basis. Default is 26
-**/
- UINT16 Idd3n;
-
-/** Offset 0x04BA - EPG DIMM Idd3P
- Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
- on a per DIMM basis. Default is 11
-**/
- UINT16 Idd3p;
-
-/** Offset 0x04BC - CMD Slew Rate Training
- Enable/Disable CMD Slew Rate Training
- $EN_DIS
-**/
- UINT8 CMDSR;
-
-/** Offset 0x04BD - CMD Drive Strength and Tx Equalization
- Enable/Disable CMD Drive Strength and Tx Equalization
- $EN_DIS
-**/
- UINT8 CMDDSEQ;
-
-/** Offset 0x04BE - CMD Normalization
- Enable/Disable CMD Normalization
- $EN_DIS
-**/
- UINT8 CMDNORM;
-
-/** Offset 0x04BF - Early DQ Write Drive Strength and Equalization Training
- Enable/Disable Early DQ Write Drive Strength and Equalization Training
- $EN_DIS
-**/
- UINT8 EWRDSEQ;
-
-/** Offset 0x04C0 - RH Activation Probability
- RH Activation Probability, Probability value is 1/2^(inputvalue)
-**/
- UINT8 RhActProbability;
-
-/** Offset 0x04C1 - RAPL PL 2 WindowX
- Power PL 2 time window X value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
-**/
- UINT8 RaplLim2WindX;
-
-/** Offset 0x04C2 - RAPL PL 2 WindowY
- Power PL 2 time window Y value, (1/1024)*(1+(x/4))*(2^y) (1=Def)
-**/
- UINT8 RaplLim2WindY;
-
-/** Offset 0x04C3 - RAPL PL 1 WindowX
- Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
-**/
- UINT8 RaplLim1WindX;
-
-/** Offset 0x04C4 - RAPL PL 1 WindowY
- Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
-**/
- UINT8 RaplLim1WindY;
-
-/** Offset 0x04C5 - RAPL PL 2 Power
- range[0;2^14-1]= [2047.875;0]in W, (222= Def)
-**/
- UINT16 RaplLim2Pwr;
-
-/** Offset 0x04C7 - RAPL PL 1 Power
- range[0;2^14-1]= [2047.875;0]in W, (0= Def)
-**/
- UINT16 RaplLim1Pwr;
-
-/** Offset 0x04C9 - Warm Threshold Ch0 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
-**/
- UINT8 WarmThresholdCh0Dimm0;
-
-/** Offset 0x04CA - Warm Threshold Ch0 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
-**/
- UINT8 WarmThresholdCh0Dimm1;
-
-/** Offset 0x04CB - Warm Threshold Ch1 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
-**/
- UINT8 WarmThresholdCh1Dimm0;
-
-/** Offset 0x04CC - Warm Threshold Ch1 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
-**/
- UINT8 WarmThresholdCh1Dimm1;
-
-/** Offset 0x04CD - Hot Threshold Ch0 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
-**/
- UINT8 HotThresholdCh0Dimm0;
-
-/** Offset 0x04CE - Hot Threshold Ch0 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
-**/
- UINT8 HotThresholdCh0Dimm1;
-
-/** Offset 0x04CF - Hot Threshold Ch1 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
-**/
- UINT8 HotThresholdCh1Dimm0;
-
-/** Offset 0x04D0 - Hot Threshold Ch1 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM. Default is 255
-**/
- UINT8 HotThresholdCh1Dimm1;
-
-/** Offset 0x04D1 - Warm Budget Ch0 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 WarmBudgetCh0Dimm0;
-
-/** Offset 0x04D2 - Warm Budget Ch0 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 WarmBudgetCh0Dimm1;
-
-/** Offset 0x04D3 - Warm Budget Ch1 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 WarmBudgetCh1Dimm0;
-
-/** Offset 0x04D4 - Warm Budget Ch1 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 WarmBudgetCh1Dimm1;
-
-/** Offset 0x04D5 - Hot Budget Ch0 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 HotBudgetCh0Dimm0;
-
-/** Offset 0x04D6 - Hot Budget Ch0 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 HotBudgetCh0Dimm1;
-
-/** Offset 0x04D7 - Hot Budget Ch1 Dimm0
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 HotBudgetCh1Dimm0;
-
-/** Offset 0x04D8 - Hot Budget Ch1 Dimm1
- range[255;0]=[31.875;0] in W for OLTM, [127.5;0] in C for CLTM
-**/
- UINT8 HotBudgetCh1Dimm1;
-
-/** Offset 0x04D9 - Idle Energy Ch0Dimm0
- Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
-**/
- UINT8 IdleEnergyCh0Dimm0;
-
-/** Offset 0x04DA - Idle Energy Ch0Dimm1
- Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
-**/
- UINT8 IdleEnergyCh0Dimm1;
-
-/** Offset 0x04DB - Idle Energy Ch1Dimm0
- Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
-**/
- UINT8 IdleEnergyCh1Dimm0;
-
-/** Offset 0x04DC - Idle Energy Ch1Dimm1
- Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
-**/
- UINT8 IdleEnergyCh1Dimm1;
-
-/** Offset 0x04DD - PowerDown Energy Ch0Dimm0
- PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
-**/
- UINT8 PdEnergyCh0Dimm0;
-
-/** Offset 0x04DE - PowerDown Energy Ch0Dimm1
- PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
-**/
- UINT8 PdEnergyCh0Dimm1;
-
-/** Offset 0x04DF - PowerDown Energy Ch1Dimm0
- PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
-**/
- UINT8 PdEnergyCh1Dimm0;
-
-/** Offset 0x04E0 - PowerDown Energy Ch1Dimm1
- PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(5= Def)
-**/
- UINT8 PdEnergyCh1Dimm1;
-
-/** Offset 0x04E1 - Activate Energy Ch0Dimm0
- Activate Energy Contribution, range[255;0],(172= Def)
-**/
- UINT8 ActEnergyCh0Dimm0;
-
-/** Offset 0x04E2 - Activate Energy Ch0Dimm1
- Activate Energy Contribution, range[255;0],(172= Def)
-**/
- UINT8 ActEnergyCh0Dimm1;
-
-/** Offset 0x04E3 - Activate Energy Ch1Dimm0
- Activate Energy Contribution, range[255;0],(172= Def)
-**/
- UINT8 ActEnergyCh1Dimm0;
-
-/** Offset 0x04E4 - Activate Energy Ch1Dimm1
- Activate Energy Contribution, range[255;0],(172= Def)
-**/
- UINT8 ActEnergyCh1Dimm1;
-
-/** Offset 0x04E5 - Read Energy Ch0Dimm0
- Read Energy Contribution, range[255;0],(212= Def)
-**/
- UINT8 RdEnergyCh0Dimm0;
-
-/** Offset 0x04E6 - Read Energy Ch0Dimm1
- Read Energy Contribution, range[255;0],(212= Def)
-**/
- UINT8 RdEnergyCh0Dimm1;
-
-/** Offset 0x04E7 - Read Energy Ch1Dimm0
- Read Energy Contribution, range[255;0],(212= Def)
-**/
- UINT8 RdEnergyCh1Dimm0;
-
-/** Offset 0x04E8 - Read Energy Ch1Dimm1
- Read Energy Contribution, range[255;0],(212= Def)
-**/
- UINT8 RdEnergyCh1Dimm1;
-
-/** Offset 0x04E9 - Write Energy Ch0Dimm0
- Write Energy Contribution, range[255;0],(221= Def)
-**/
- UINT8 WrEnergyCh0Dimm0;
-
-/** Offset 0x04EA - Write Energy Ch0Dimm1
- Write Energy Contribution, range[255;0],(221= Def)
-**/
- UINT8 WrEnergyCh0Dimm1;
-
-/** Offset 0x04EB - Write Energy Ch1Dimm0
- Write Energy Contribution, range[255;0],(221= Def)
-**/
- UINT8 WrEnergyCh1Dimm0;
-
-/** Offset 0x04EC - Write Energy Ch1Dimm1
- Write Energy Contribution, range[255;0],(221= Def)
-**/
- UINT8 WrEnergyCh1Dimm1;
-
-/** Offset 0x04ED - Throttler CKEMin Timer
- Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
- Default is 0x30
-**/
- UINT8 ThrtCkeMinTmr;
-
-/** Offset 0x04EE - Cke Rank Mapping
- Bits [7:4] - Channel 1, bits [3:0] - Channel 0. <b>0xAA=Default</b> Bit [i] specifies
- which rank CKE[i] goes to.
-**/
- UINT8 CkeRankMapping;
-
-/** Offset 0x04EF - Rapl Power Floor Ch0
- Power budget ,range[255;0],(0= 5.3W Def)
-**/
- UINT8 RaplPwrFlCh0;
-
-/** Offset 0x04F0 - Rapl Power Floor Ch1
- Power budget ,range[255;0],(0= 5.3W Def)
-**/
- UINT8 RaplPwrFlCh1;
-
-/** Offset 0x04F1 - Command Rate Support
- CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
- 0:Disable, 1:1 CMD, 2:2 CMDS, 3:3 CMDS, 4:4 CMDS, 5:5 CMDS, 6:6 CMDS, 7:7 CMDS
-**/
- UINT8 EnCmdRate;
-
-/** Offset 0x04F2 - REFRESH_2X_MODE
- 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
- 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
-**/
- UINT8 Refresh2X;
-
-/** Offset 0x04F3 - Energy Performance Gain
- Enable/disable(default) Energy Performance Gain.
- $EN_DIS
-**/
- UINT8 EpgEnable;
-
-/** Offset 0x04F4 - Row Hammer Solution
- Type of method used to prevent Row Hammer. Default is Hardware RHP
- 0:Hardware RHP, 1:2x Refresh
-**/
- UINT8 RhSolution;
-
-/** Offset 0x04F5 - User Manual Threshold
- Disabled: Predefined threshold will be used.\n
- Enabled: User Input will be used.
- $EN_DIS
-**/
- UINT8 UserThresholdEnable;
-
-/** Offset 0x04F6 - User Manual Budget
- Disabled: Configuration of memories will defined the Budget value.\n
- Enabled: User Input will be used.
- $EN_DIS
-**/
- UINT8 UserBudgetEnable;
-
-/** Offset 0x04F7 - TcritMax
- Maximum Critical Temperature in Centigrade of the On-DIMM Thermal Sensor. TCRITMax
- has to be greater than THIGHMax .\n
- Critical temperature will be TcritMax
-**/
- UINT8 TsodTcritMax;
-
-/** Offset 0x04F8 - Event mode
- Disable:Comparator mode.\n
- Enable:Interrupt mode
- $EN_DIS
-**/
- UINT8 TsodEventMode;
-
-/** Offset 0x04F9 - EVENT polarity
- Disable:Active LOW.\n
- Enable:Active HIGH
- $EN_DIS
-**/
- UINT8 TsodEventPolarity;
-
-/** Offset 0x04FA - Critical event only
- Disable:Trips on alarm or critical.\n
- Enable:Trips only if criticaal temperature is reached
- $EN_DIS
-**/
- UINT8 TsodCriticalEventOnly;
-
-/** Offset 0x04FB - Event output control
- Disable:Event output disable.\n
- Enable:Event output enabled
- $EN_DIS
-**/
- UINT8 TsodEventOutputControl;
-
-/** Offset 0x04FC - Alarm window lock bit
- Disable:Alarm trips are not locked and can be changed.\n
- Enable:Alarm trips are locked and cannot be changed
- $EN_DIS
-**/
- UINT8 TsodAlarmwindowLockBit;
-
-/** Offset 0x04FD - Critical trip lock bit
- Disable:Critical trip is not locked and can be changed.\n
- Enable:Critical trip is locked and cannot be changed
- $EN_DIS
-**/
- UINT8 TsodCriticaltripLockBit;
-
-/** Offset 0x04FE - Shutdown mode
- Disable:Temperature sensor enable.\n
- Enable:Temperature sensor disable
- $EN_DIS
-**/
- UINT8 TsodShutdownMode;
-
-/** Offset 0x04FF - ThighMax
- Thigh = ThighMax (Default is 93)
-**/
- UINT8 TsodThigMax;
-
-/** Offset 0x0500 - User Manual Thig and Tcrit
- Disabled(Default): Temperature will be given by the configuration of memories and
- 1x or 2xrefresh rate.\n
- Enabled: User Input will define for Thigh and Tcrit.
- $EN_DIS
-**/
- UINT8 TsodManualEnable;
-
-/** Offset 0x0501 - Force OLTM or 2X Refresh when needed
- Disabled(Default): = Force OLTM.\n
- Enabled: = Force 2x Refresh.
- $EN_DIS
-**/
- UINT8 ForceOltmOrRefresh2x;
-
-/** Offset 0x0502 - Pwr Down Idle Timer
- The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
- AUTO: 64 for ULX/ULT, 128 for DT/Halo
-**/
- UINT8 PwdwnIdleCounter;
-
-/** Offset 0x0503 - Bitmask of ranks that have CA bus terminated
- Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
- Rank0 is terminating and Rank1 is non-terminating</b>
-**/
- UINT8 CmdRanksTerminated;
-
-/** Offset 0x0504 - GDXC MOT enable
- GDXC MOT enable.
- $EN_DIS
-**/
- UINT8 GdxcEnable;
-
-/** Offset 0x0505 - PcdSerialDebugLevel
- Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
- Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
- Info & Verbose.
- 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
- Error Warnings and Info, 5:Load Error Warnings Info and Verbose
-**/
- UINT8 PcdSerialDebugLevel;
-
-/** Offset 0x0506 - Fivr Faults
- Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
- $EN_DIS
-**/
- UINT8 FivrFaults;
-
-/** Offset 0x0507 - Fivr Efficiency
- Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
- $EN_DIS
-**/
- UINT8 FivrEfficiency;
-
-/** Offset 0x0508 - Safe Mode Support
- This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
- $EN_DIS
-**/
- UINT8 SafeMode;
-
-/** Offset 0x0509 - Ask MRC to clear memory content
- Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
- $EN_DIS
-**/
- UINT8 CleanMemory;
-
-/** Offset 0x050A - LpDdrDqDqsReTraining
- Enables/Disable LpDdrDqDqsReTraining
- $EN_DIS
-**/
- UINT8 LpDdrDqDqsReTraining;
-
-/** Offset 0x050B - Post Code Output Port
- This option configures Post Code Output Port
-**/
- UINT16 PostCodeOutputPort;
-
-/** Offset 0x050D - RMTLoopCount
- Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
-**/
- UINT8 RMTLoopCount;
-
-/** Offset 0x050E - BER Support
- Enable/Disable the Rank Margin Tool interpolation/extrapolation.
- 0:Disable, 1:Enable
-**/
- UINT8 EnBER;
-
-/** Offset 0x050F - Dual Dimm Per-Channel Board Type
- Option to indicate if Board Layout includes One/Two DIMMs per channel. This is used
- to limit maximum frequency for some SKUs.
- 0:1DPC, 1:2DPC
-**/
- UINT8 DualDimmPerChannelBoardType;
-
-/** Offset 0x0510 - DDR4 Mixed U-DIMM 2DPC Limitation
- Enable/Disable 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population.
- Disable(Default)=0, Enable=1
- $EN_DIS
-**/
- UINT8 Ddr4MixedUDimm2DpcLimit;
-
-/** Offset 0x0511 - CFL Reserved
- Reserved FspmConfig CFL
- $EN_DIS
-**/
- UINT8 ReservedFspmUpdCfl[2];
-
-/** Offset 0x0513 - Memory Test on Warm Boot
- Run Base Memory Test on Warm Boot
- 0:Disable, 1:Enable
-**/
- UINT8 MemTestOnWarmBoot;
-
-/** Offset 0x0514 - Throttler CKEMin Timer - LPDDR
- Timer value for CKEMin (For LPDDR Only), range[255;0]. Req'd min of SC_ROUND_T +
- BYTE_LENGTH (4). Default is 0x40
-**/
- UINT8 ThrtCkeMinTmrLpddr;
-
-/** Offset 0x0515
-**/
- UINT8 ReservedFspmUpd[10];
-} FSP_M_CONFIG;
-
-/** Fsp M Test Configuration
-**/
-typedef struct {
-
-/** Offset 0x0520
-**/
- UINT32 Signature;
-
-/** Offset 0x0524 - Skip external display device scanning
- Enable: Do not scan for external display device, Disable (Default): Scan external
- display devices
- $EN_DIS
-**/
- UINT8 SkipExtGfxScan;
-
-/** Offset 0x0525 - Generate BIOS Data ACPI Table
- Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
- $EN_DIS
-**/
- UINT8 BdatEnable;
-
-/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM
- Detect and report if external graphics device only support LegacyOpROM or not (to
- support CSM auto-enable). Enable(Default)=1, Disable=0
- $EN_DIS
-**/
- UINT8 ScanExtGfxForLegacyOpRom;
-
-/** Offset 0x0527 - Lock PCU Thermal Management registers
- Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
- $EN_DIS
-**/
- UINT8 LockPTMregs;
-
-/** Offset 0x0528 - DMI Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 DmiMaxLinkSpeed;
-
-/** Offset 0x0529 - DMI Equalization Phase 2
- DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
- AUTO - Use the current default method
- 0:Disable phase2, 1:Enable phase2, 2:Auto
-**/
- UINT8 DmiGen3EqPh2Enable;
-
-/** Offset 0x052A - DMI Gen3 Equalization Phase3
- DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 DmiGen3EqPh3Method;
-
-/** Offset 0x052B - Phase2 EQ enable on the PEG 0:1:0.
- Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
- Enable phase 2, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Peg0Gen3EqPh2Enable;
-
-/** Offset 0x052C - Phase2 EQ enable on the PEG 0:1:1.
- Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
- Enable phase 2, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Peg1Gen3EqPh2Enable;
-
-/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:2.
- Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
- Enable phase 2, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Peg2Gen3EqPh2Enable;
-
-/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:3.
- Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
- Enable phase 2, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Peg3Gen3EqPh2Enable;
-
-/** Offset 0x052F - Phase3 EQ method on the PEG 0:1:0.
- PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 Peg0Gen3EqPh3Method;
-
-/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:1.
- PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 Peg1Gen3EqPh3Method;
-
-/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:2.
- PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 Peg2Gen3EqPh3Method;
-
-/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:3.
- PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 Peg3Gen3EqPh3Method;
-
-/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
- Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
- Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
- $EN_DIS
-**/
- UINT8 PegGen3ProgramStaticEq;
-
-/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt
- Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):
- Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test
- and generate new EQ values every boot, not recommended
- 0:Disable, 1:Enable
-**/
- UINT8 Gen3SwEqAlwaysAttempt;
-
-/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq
- Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test
- Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the
- current default method (Default)Auto will test Presets 7, 3, and 5. It is possible
- for this default to change over time;using Auto will ensure Reference Code always
- uses the latest default settings
- 0:P7 P3 P5, 1:P0 to P9, 2:Auto
-**/
- UINT8 Gen3SwEqNumberOfPresets;
-
-/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
- Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization
- Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):
- Use the current default
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Gen3SwEqEnableVocTest;
-
-/** Offset 0x0537 - PCIe Rx Compliance Testing Mode
- Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
- PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
- it should only be set when doing PCIe compliance testing
- $EN_DIS
-**/
- UINT8 PegRxCemTestingMode;
-
-/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled
- the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0
-**/
- UINT8 PegRxCemLoopbackLane;
-
-/** Offset 0x0539 - Generate PCIe BDAT Margin Table
- Set this policy to enable the generation and addition of PCIe margin data to the
- BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin
- data generation, Enable(0x1): Generate PCIe BDAT margin data
- $EN_DIS
-**/
- UINT8 PegGenerateBdatMarginTable;
-
-/** Offset 0x053A - PCIe Non-Protocol Awareness for Rx Compliance Testing
- Set this policy to enable the generation and addition of PCIe margin data to the
- BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,
- Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for
- compliance testing
- $EN_DIS
-**/
- UINT8 PegRxCemNonProtocolAwareness;
-
-/** Offset 0x053B - PCIe Override RxCTLE
- Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
- Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
- peak values unmodified
- $EN_DIS
-**/
- UINT8 PegGen3RxCtleOverride;
-
-/** Offset 0x053C - Rsvd
- Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
- Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
- peak values unmodified
- $EN_DIS
-**/
- UINT8 PegGen3Rsvd;
-
-/** Offset 0x053D - PEG Gen3 Root port preset values per lane
- Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
-**/
- UINT8 PegGen3RootPortPreset[20];
-
-/** Offset 0x0551 - PEG Gen3 End port preset values per lane
- Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
-**/
- UINT8 PegGen3EndPointPreset[20];
-
-/** Offset 0x0565 - PEG Gen3 End port Hint values per lane
- Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
-**/
- UINT8 PegGen3EndPointHint[20];
-
-/** Offset 0x0579
-**/
- UINT8 UnusedUpdSpace8;
-
-/** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization
- Range: 0-65535, default is 1000. @warning Do not change from the default
-**/
- UINT16 Gen3SwEqJitterDwellTime;
-
-/** Offset 0x057C - Jitter Error Target for PCIe Gen3 Software Equalization
- Range: 0-65535, default is 1. @warning Do not change from the default
-**/
- UINT16 Gen3SwEqJitterErrorTarget;
-
-/** Offset 0x057E - VOC Dwell Time for PCIe Gen3 Software Equalization
- Range: 0-65535, default is 10000. @warning Do not change from the default
-**/
- UINT16 Gen3SwEqVocDwellTime;
-
-/** Offset 0x0580 - VOC Error Target for PCIe Gen3 Software Equalization
- Range: 0-65535, default is 2. @warning Do not change from the default
-**/
- UINT16 Gen3SwEqVocErrorTarget;
-
-/** Offset 0x0582 - Panel Power Enable
- Control for enabling/disabling VDD force bit (Required only for early enabling of
- eDP panel). 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 PanelPowerEnable;
-
-/** Offset 0x0583 - BdatTestType
- Indicates the type of Memory Training data to populate into the BDAT ACPI table.
- 0:Rank Margin Tool, 1:Margin2D
-**/
- UINT8 BdatTestType;
-
-/** Offset 0x0584 - SaPreMemTestRsvd
- Reserved for SA Pre-Mem Test
- $EN_DIS
-**/
- UINT8 SaPreMemTestRsvd[12];
-
-/** Offset 0x0590 - TotalFlashSize
- Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
-**/
- UINT16 TotalFlashSize;
-
-/** Offset 0x0592 - BiosSize
- Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
-**/
- UINT16 BiosSize;
-
-/** Offset 0x0594 - TxtAcheckRequest
- Enable/Disable. When Enabled, it will forcing calling TXT Acheck once.
- $EN_DIS
-**/
- UINT8 TxtAcheckRequest;
-
-/** Offset 0x0595 - SecurityTestRsvd
- Reserved for SA Pre-Mem Test
- $EN_DIS
-**/
- UINT8 SecurityTestRsvd[3];
-
-/** Offset 0x0598 - Smbus dynamic power gating
- Disable or Enable Smbus dynamic power gating.
- $EN_DIS
-**/
- UINT8 SmbusDynamicPowerGating;
-
-/** Offset 0x0599 - Disable and Lock Watch Dog Register
- Set 1 to clear WDT status, then disable and lock WDT registers.
- $EN_DIS
-**/
- UINT8 WdtDisableAndLock;
-
-/** Offset 0x059A - SMBUS SPD Write Disable
- Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
- Disable bit. For security recommendations, SPD write disable bit must be set.
- $EN_DIS
-**/
- UINT8 SmbusSpdWriteDisable;
-
-/** Offset 0x059B - ChipsetInit HECI message
- DEPRECATED
- $EN_DIS
-**/
- UINT8 ChipsetInitMessage;
-
-/** Offset 0x059C - Bypass ChipsetInit sync reset.
- DEPRECATED
- $EN_DIS
-**/
- UINT8 BypassPhySyncReset;
-
-/** Offset 0x059D - Force ME DID Init Status
- Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
- ME DID init stat value
- $EN_DIS
-**/
- UINT8 DidInitStat;
-
-/** Offset 0x059E - CPU Replaced Polling Disable
- Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
- $EN_DIS
-**/
- UINT8 DisableCpuReplacedPolling;
-
-/** Offset 0x059F - ME DID Message
- Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
- the DID message from being sent)
- $EN_DIS
-**/
- UINT8 SendDidMsg;
-
-/** Offset 0x05A0 - Retry mechanism for HECI APIs
- Test, 0: disable, 1: enable, Enable/Disable HECI retry.
- $EN_DIS
-**/
- UINT8 DisableHeciRetry;
-
-/** Offset 0x05A1 - Check HECI message before send
- Test, 0: disable, 1: enable, Enable/Disable message check.
- $EN_DIS
-**/
- UINT8 DisableMessageCheck;
-
-/** Offset 0x05A2 - Skip MBP HOB
- Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
- $EN_DIS
-**/
- UINT8 SkipMbpHob;
-
-/** Offset 0x05A3 - HECI2 Interface Communication
- Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
- $EN_DIS
-**/
- UINT8 HeciCommunication2;
-
-/** Offset 0x05A4 - Enable KT device
- Test, 0: disable, 1: enable, Enable or Disable KT device.
- $EN_DIS
-**/
- UINT8 KtDeviceEnable;
-
-/** Offset 0x05A5 - tRd2RdSG
- Delay between Read-to-Read commands in the same Bank Group. 0-Auto, Range 4-54.
-**/
- UINT8 tRd2RdSG;
-
-/** Offset 0x05A6 - tRd2RdDG
- Delay between Read-to-Read commands in different Bank Group for DDR4. All other
- DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
-**/
- UINT8 tRd2RdDG;
-
-/** Offset 0x05A7 - tRd2RdDR
- Delay between Read-to-Read commands in different Ranks. 0-Auto, Range 4-54.
-**/
- UINT8 tRd2RdDR;
-
-/** Offset 0x05A8 - tRd2RdDD
- Delay between Read-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
-**/
- UINT8 tRd2RdDD;
-
-/** Offset 0x05A9 - tWr2RdSG
- Delay between Write-to-Read commands in the same Bank Group. 0-Auto, Range 4-86.
-**/
- UINT8 tWr2RdSG;
-
-/** Offset 0x05AA - tWr2RdDG
- Delay between Write-to-Read commands in different Bank Group for DDR4. All other
- DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
-**/
- UINT8 tWr2RdDG;
-
-/** Offset 0x05AB - tWr2RdDR
- Delay between Write-to-Read commands in different Ranks. 0-Auto, Range 4-54.
-**/
- UINT8 tWr2RdDR;
-
-/** Offset 0x05AC - tWr2RdDD
- Delay between Write-to-Read commands in different DIMMs. 0-Auto, Range 4-54.
-**/
- UINT8 tWr2RdDD;
-
-/** Offset 0x05AD - tWr2WrSG
- Delay between Write-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
-**/
- UINT8 tWr2WrSG;
-
-/** Offset 0x05AE - tWr2WrDG
- Delay between Write-to-Write commands in different Bank Group for DDR4. All other
- DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
-**/
- UINT8 tWr2WrDG;
-
-/** Offset 0x05AF - tWr2WrDR
- Delay between Write-to-Write commands in different Ranks. 0-Auto, Range 4-54.
-**/
- UINT8 tWr2WrDR;
-
-/** Offset 0x05B0 - tWr2WrDD
- Delay between Write-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
-**/
- UINT8 tWr2WrDD;
-
-/** Offset 0x05B1 - tRd2WrSG
- Delay between Read-to-Write commands in the same Bank Group. 0-Auto, Range 4-54.
-**/
- UINT8 tRd2WrSG;
-
-/** Offset 0x05B2 - tRd2WrDG
- Delay between Read-to-Write commands in different Bank Group for DDR4. All other
- DDR technologies should set this equal to SG. 0-Auto, Range 4-54.
-**/
- UINT8 tRd2WrDG;
-
-/** Offset 0x05B3 - tRd2WrDR
- Delay between Read-to-Write commands in different Ranks. 0-Auto, Range 4-54.
-**/
- UINT8 tRd2WrDR;
-
-/** Offset 0x05B4 - tRd2WrDD
- Delay between Read-to-Write commands in different DIMMs. 0-Auto, Range 4-54.
-**/
- UINT8 tRd2WrDD;
-
-/** Offset 0x05B5 - tRRD_L
- Min Row Active to Row Active Delay Time for Same Bank Group, DDR4 Only. 0: AUTO, max: 31
-**/
- UINT8 tRRD_L;
-
-/** Offset 0x05B6 - tRRD_S
- Min Row Active to Row Active Delay Time for Different Bank Group, DDR4 Only. 0:
- AUTO, max: 31
-**/
- UINT8 tRRD_S;
-
-/** Offset 0x05B7 - tWTR_L
- Min Internal Write to Read Command Delay Time for Same Bank Group, DDR4 Only. 0:
- AUTO, max: 60
-**/
- UINT8 tWTR_L;
-
-/** Offset 0x05B8 - tWTR_S
- Min Internal Write to Read Command Delay Time for Different Bank Group, DDR4 Only.
- 0: AUTO, max: 28
-**/
- UINT8 tWTR_S;
-
-/** Offset 0x05B9
-**/
- UINT8 ReservedFspmTestUpd[3];
-} FSP_M_TEST_CONFIG;
-
-/** Fsp M UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPM_ARCH_UPD FspmArchUpd;
-
-/** Offset 0x0040
-**/
- FSP_M_CONFIG FspmConfig;
-
-/** Offset 0x051F
-**/
- UINT8 UnusedUpdSpace7;
-
-/** Offset 0x0520
-**/
- FSP_M_TEST_CONFIG FspmTestConfig;
-
-/** Offset 0x05BC
-**/
- UINT32 UpdTerminator;
-} FSPM_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
deleted file mode 100644
index 653e669b4a..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FspsUpd.h
+++ /dev/null
@@ -1,3318 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-///
-/// Azalia Header structure
-///
-typedef struct {
- UINT16 VendorId; ///< Codec Vendor ID
- UINT16 DeviceId; ///< Codec Device ID
- UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
- UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
- UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
- UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
-} AZALIA_HEADER;
-
-///
-/// Audio Azalia Verb Table structure
-///
-typedef struct {
- AZALIA_HEADER Header; ///< AZALIA PCH header
- UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
-} AUDIO_AZALIA_VERB_TABLE;
-
-///
-/// Refer to the definition of PCH_INT_PIN
-///
-typedef enum {
- SiPchNoInt, ///< No Interrupt Pin
- SiPchIntA,
- SiPchIntB,
- SiPchIntC,
- SiPchIntD
-} SI_PCH_INT_PIN;
-///
-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
-///
-typedef struct {
- UINT8 Device; ///< Device number
- UINT8 Function; ///< Device function
- UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
- UINT8 Irq; ///< IRQ to be set for device.
-} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-
-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
-
-
-/** Fsp S Configuration
-**/
-typedef struct {
-
-/** Offset 0x0020 - Logo Pointer
- Points to PEI Display Logo Image
-**/
- UINT32 LogoPtr;
-
-/** Offset 0x0024 - Logo Size
- Size of PEI Display Logo Image
-**/
- UINT32 LogoSize;
-
-/** Offset 0x0028 - Graphics Configuration Ptr
- Points to VBT
-**/
- UINT32 GraphicsConfigPtr;
-
-/** Offset 0x002C - Enable Device 4
- Enable/disable Device 4
- $EN_DIS
-**/
- UINT8 Device4Enable;
-
-/** Offset 0x002D - Enable HD Audio DSP
- Enable/disable HD Audio DSP feature.
- $EN_DIS
-**/
- UINT8 PchHdaDspEnable;
-
-/** Offset 0x002E
-**/
- UINT8 UnusedUpdSpace0[3];
-
-/** Offset 0x0031 - Enable eMMC Controller
- Enable/disable eMMC Controller.
- $EN_DIS
-**/
- UINT8 ScsEmmcEnabled;
-
-/** Offset 0x0032 - Enable eMMC HS400 Mode
- Enable eMMC HS400 Mode.
- $EN_DIS
-**/
- UINT8 ScsEmmcHs400Enabled;
-
-/** Offset 0x0033 - Enable SdCard Controller
- Enable/disable SD Card Controller.
- $EN_DIS
-**/
- UINT8 ScsSdCardEnabled;
-
-/** Offset 0x0034 - Show SPI controller
- Enable/disable to show SPI controller.
- $EN_DIS
-**/
- UINT8 ShowSpiController;
-
-/** Offset 0x0035
-**/
- UINT8 UnusedUpdSpace1[3];
-
-/** Offset 0x0038 - MicrocodeRegionBase
- Memory Base of Microcode Updates
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x003C - MicrocodeRegionSize
- Size of Microcode Updates
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0040 - Turbo Mode
- Enable/Disable Turbo mode. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 TurboMode;
-
-/** Offset 0x0041 - Enable SATA SALP Support
- Enable/disable SATA Aggressive Link Power Management.
- $EN_DIS
-**/
- UINT8 SataSalpSupport;
-
-/** Offset 0x0042 - Enable SATA ports
- Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
- and so on.
-**/
- UINT8 SataPortsEnable[8];
-
-/** Offset 0x004A - Enable SATA DEVSLP Feature
- Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
- port, byte0 for port0, byte1 for port1, and so on.
-**/
- UINT8 SataPortsDevSlp[8];
-
-/** Offset 0x0052 - Enable USB2 ports
- Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb20Enable[16];
-
-/** Offset 0x0062 - Enable USB3 ports
- Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb30Enable[10];
-
-/** Offset 0x006C - Enable xDCI controller
- Enable/disable to xDCI controller.
- $EN_DIS
-**/
- UINT8 XdciEnable;
-
-/** Offset 0x006D
-**/
- UINT8 UnusedUpdSpace2[2];
-
-/** Offset 0x006F - Enable SerialIo Device Mode
- 0:Disabled, 1:PCI Mode, 2:Acpi mode, 3:Hidden mode (Legacy UART mode) - Enable/disable
- SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,SPI2,UART0,UART1,UART2 device
- mode respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1,
- and so on.
-**/
- UINT8 SerialIoDevMode[12];
-
-/** Offset 0x007B - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
- The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
-**/
- UINT32 DevIntConfigPtr;
-
-/** Offset 0x007F - Number of DevIntConfig Entry
- Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
- must not be NULL.
-**/
- UINT8 NumOfDevIntConfig;
-
-/** Offset 0x0080 - PIRQx to IRQx Map Config
- PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
- PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
- 8259 PCI mode.
-**/
- UINT8 PxRcConfig[8];
-
-/** Offset 0x0088 - Select GPIO IRQ Route
- GPIO IRQ Select. The valid value is 14 or 15.
-**/
- UINT8 GpioIrqRoute;
-
-/** Offset 0x0089 - Select SciIrqSelect
- SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
-**/
- UINT8 SciIrqSelect;
-
-/** Offset 0x008A - Select TcoIrqSelect
- TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
-**/
- UINT8 TcoIrqSelect;
-
-/** Offset 0x008B - Enable/Disable Tco IRQ
- Enable/disable TCO IRQ
- $EN_DIS
-**/
- UINT8 TcoIrqEnable;
-
-/** Offset 0x008C - PCH HDA Verb Table Entry Number
- Number of Entries in Verb Table.
-**/
- UINT8 PchHdaVerbTableEntryNum;
-
-/** Offset 0x008D - PCH HDA Verb Table Pointer
- Pointer to Array of pointers to Verb Table.
-**/
- UINT32 PchHdaVerbTablePtr;
-
-/** Offset 0x0091 - PCH HDA Codec Sx Wake Capability
- Capability to detect wake initiated by a codec in Sx
-**/
- UINT8 PchHdaCodecSxWakeCapability;
-
-/** Offset 0x0092 - Enable SATA
- Enable/disable SATA controller.
- $EN_DIS
-**/
- UINT8 SataEnable;
-
-/** Offset 0x0093 - SATA Mode
- Select SATA controller working mode.
- 0:AHCI, 1:RAID
-**/
- UINT8 SataMode;
-
-/** Offset 0x0094 - USB Per Port HS Preemphasis Bias
- USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
-**/
- UINT8 Usb2AfePetxiset[16];
-
-/** Offset 0x00A4 - USB Per Port HS Transmitter Bias
- USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
-**/
- UINT8 Usb2AfeTxiset[16];
-
-/** Offset 0x00B4 - USB Per Port HS Transmitter Emphasis
- USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
- 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
-**/
- UINT8 Usb2AfePredeemp[16];
-
-/** Offset 0x00C4 - USB Per Port Half Bit Pre-emphasis
- USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
- One byte for each port.
-**/
- UINT8 Usb2AfePehalfbit[16];
-
-/** Offset 0x00D4 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
- Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmphEnable[10];
-
-/** Offset 0x00DE - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
- USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
- <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmph[10];
-
-/** Offset 0x00E8 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
- Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmpEnable[10];
-
-/** Offset 0x00F2 - USB 3.0 TX Output Downscale Amplitude Adjustment
- USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
- = 00h</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmp[10];
-
-/** Offset 0x00FC - Enable LAN
- Enable/disable LAN controller.
- $EN_DIS
-**/
- UINT8 PchLanEnable;
-
-/** Offset 0x00FD - Enable HD Audio Link
- Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkHda;
-
-/** Offset 0x00FE - Enable HD Audio DMIC0 Link
- Enable/disable HD Audio DMIC0 link. Muxed with SNDW4.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkDmic0;
-
-/** Offset 0x00FF - Enable HD Audio DMIC1 Link
- Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkDmic1;
-
-/** Offset 0x0100 - Enable HD Audio SSP0 Link
- Enable/disable HD Audio SSP0/I2S link. Muxed with HDA.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkSsp0;
-
-/** Offset 0x0101 - Enable HD Audio SSP1 Link
- Enable/disable HD Audio SSP1/I2S link. Muxed with HDA/SNDW2.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkSsp1;
-
-/** Offset 0x0102 - Enable HD Audio SSP2 Link
- Enable/disable HD Audio SSP2/I2S link.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkSsp2;
-
-/** Offset 0x0103 - Enable HD Audio SoundWire#1 Link
- Enable/disable HD Audio SNDW1 link. Muxed with HDA.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkSndw1;
-
-/** Offset 0x0104 - Enable HD Audio SoundWire#2 Link
- Enable/disable HD Audio SNDW2 link. Muxed with SSP1.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkSndw2;
-
-/** Offset 0x0105 - Enable HD Audio SoundWire#3 Link
- Enable/disable HD Audio SNDW3 link. Muxed with DMIC1.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkSndw3;
-
-/** Offset 0x0106 - Enable HD Audio SoundWire#4 Link
- Enable/disable HD Audio SNDW4 link. Muxed with DMIC0.
- $EN_DIS
-**/
- UINT8 PchHdaAudioLinkSndw4;
-
-/** Offset 0x0107 - Soundwire Clock Buffer GPIO RCOMP Setting
- 0: non-ACT - 50 Ohm driver impedance, 1: ACT - 8 Ohm driver impedance.
- $EN_DIS
-**/
- UINT8 PchHdaSndwBufferRcomp;
-
-/** Offset 0x0108 - PTM for PCIE RP Mask
- Enable/disable Precision Time Measurement for PCIE Root Ports. 0: disable, 1: enable.
- One bit for each port, bit0 for port1, bit1 for port2, and so on.
-**/
- UINT32 PcieRpPtmMask;
-
-/** Offset 0x010C - DPC for PCIE RP Mask
- Enable/disable Downstream Port Containment for PCIE Root Ports. 0: disable, 1: enable.
- One bit for each port, bit0 for port1, bit1 for port2, and so on.
-**/
- UINT32 PcieRpDpcMask;
-
-/** Offset 0x0110 - DPC Extensions PCIE RP Mask
- Enable/disable DPC Extensions for PCIE Root Ports. 0: disable, 1: enable. One bit
- for each port, bit0 for port1, bit1 for port2, and so on.
-**/
- UINT32 PcieRpDpcExtensionsMask;
-
-/** Offset 0x0114 - USB PDO Programming
- Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
- during later phase. 1: enable, 0: disable
- $EN_DIS
-**/
- UINT8 UsbPdoProgramming;
-
-/** Offset 0x0115 - Power button debounce configuration
- Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
- be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
-**/
- UINT32 PmcPowerButtonDebounce;
-
-/** Offset 0x0119 - PCH eSPI Master and Slave BME enabled
- PCH eSPI Master and Slave BME enabled
- $EN_DIS
-**/
- UINT8 PchEspiBmeMasterSlaveEnabled;
-
-/** Offset 0x011A - PCH SATA use RST Legacy OROM
- Use PCH SATA RST Legacy OROM when CSM is Enabled
- $EN_DIS
-**/
- UINT8 SataRstLegacyOrom;
-
-/** Offset 0x011B - Trace Hub Memory Base
- If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
- trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
- memory is configured properly.
-**/
- UINT32 TraceHubMemBase;
-
-/** Offset 0x011F - PMC Debug Message Enable
- When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
- will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
- $EN_DIS
-**/
- UINT8 PmcDbgMsgEn;
-
-/** Offset 0x0120 - Pointer of ChipsetInit Binary
- ChipsetInit Binary Pointer.
-**/
- UINT32 ChipsetInitBinPtr;
-
-/** Offset 0x0124 - Length of ChipsetInit Binary
- ChipsetInit Binary Length.
-**/
- UINT32 ChipsetInitBinLen;
-
-/** Offset 0x0128 - PchPostMemRsvd
- Reserved for PCH Post-Mem
- $EN_DIS
-**/
- UINT8 PchPostMemRsvd[29];
-
-/** Offset 0x0145 - Enable Ufs Controller
- Enable/disable Ufs 2.0 Controller.
- $EN_DIS
-**/
- UINT8 ScsUfsEnabled;
-
-/** Offset 0x0146 - CNVi Configuration
- This option allows for automatic detection of Connectivity Solution. [Auto Detection]
- assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
- 0:Disable, 1:Auto
-**/
- UINT8 PchCnviMode;
-
-/** Offset 0x0147 - SdCard power enable polarity
- Choose SD_PWREN# polarity
- 0: Active low, 1: Active high
-**/
- UINT8 SdCardPowerEnableActiveHigh;
-
-/** Offset 0x0148 - PCH USB2 PHY Power Gating enable
- 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
- Sus Well PG
- $EN_DIS
-**/
- UINT8 PchUsb2PhySusPgEnable;
-
-/** Offset 0x0149 - PCH USB OverCurrent mapping enable
- 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
- mapping allow for NOA usage of OC pins
- $EN_DIS
-**/
- UINT8 PchUsbOverCurrentEnable;
-
-/** Offset 0x014A
-**/
- UINT8 UnusedUpdSpace3;
-
-/** Offset 0x014B - CNVi MfUart1 Type
- This option configures Uart type which connects to MfUart1
- 0:ISH Uart0, 1:SerialIO Uart2, 2:Uart over external pads
-**/
- UINT8 PchCnviMfUart1Type;
-
-/** Offset 0x014C - Espi Lgmr Memory Range decode
- This option enables or disables espi lgmr
- $EN_DIS
-**/
- UINT8 PchEspiLgmrEnable;
-
-/** Offset 0x014D - HECI3 state
- The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
- 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 Heci3Enabled;
-
-/** Offset 0x014E
-**/
- UINT8 UnusedUpdSpace4;
-
-/** Offset 0x014F - PCHHOT# pin
- Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PchHotEnable;
-
-/** Offset 0x0150 - SATA LED
- SATA LED indicating SATA controller activity. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 SataLedEnable;
-
-/** Offset 0x0151 - VRAlert# Pin
- When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
- to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PchPmVrAlert;
-
-/** Offset 0x0152 - SLP_S0 VM Dynamic Control
- SLP_S0 Voltage Margining Runtime Control Policy. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PchPmSlpS0VmRuntimeControl;
-
-/** Offset 0x0153 - SLP_S0 VM 0.70V Support
- SLP_S0 Voltage Margining 0.70V Support Policy. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PchPmSlpS0Vm070VSupport;
-
-/** Offset 0x0154 - SLP_S0 VM 0.75V Support
- SLP_S0 Voltage Margining 0.75V Support Policy. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PchPmSlpS0Vm075VSupport;
-
-/** Offset 0x0155 - AMT Switch
- Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
- $EN_DIS
-**/
- UINT8 AmtEnabled;
-
-/** Offset 0x0156 - WatchDog Timer Switch
- Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.
- $EN_DIS
-**/
- UINT8 WatchDog;
-
-/** Offset 0x0157 - ASF Switch
- Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.
- $EN_DIS
-**/
- UINT8 AsfEnabled;
-
-/** Offset 0x0158 - Manageability Mode set by Mebx
- Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
- $EN_DIS
-**/
- UINT8 ManageabilityMode;
-
-/** Offset 0x0159 - PET Progress
- Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
- PET Events.
- $EN_DIS
-**/
- UINT8 FwProgress;
-
-/** Offset 0x015A - SOL Switch
- Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
- $EN_DIS
-**/
- UINT8 AmtSolEnabled;
-
-/** Offset 0x015B - OS Timer
- 16 bits Value, Set OS watchdog timer.
- $EN_DIS
-**/
- UINT16 WatchDogTimerOs;
-
-/** Offset 0x015D - BIOS Timer
- 16 bits Value, Set BIOS watchdog timer.
- $EN_DIS
-**/
- UINT16 WatchDogTimerBios;
-
-/** Offset 0x015F - Remote Assistance Trigger Availablilty
- Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx
- $EN_DIS
-**/
- UINT8 RemoteAssistance;
-
-/** Offset 0x0160 - KVM Switch
- Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx
- $EN_DIS
-**/
- UINT8 AmtKvmEnabled;
-
-/** Offset 0x0161 - MEBX execution
- Enable/Disable. 0: Disable, 1: enable, Force MEBX execution
- $EN_DIS
-**/
- UINT8 ForcMebxSyncUp;
-
-/** Offset 0x0162
-**/
- UINT8 UnusedUpdSpace5[1];
-
-/** Offset 0x0163 - PCH PCIe root port connection type
- 0: built-in device, 1:slot
-**/
- UINT8 PcieRpSlotImplemented[24];
-
-/** Offset 0x017B - Usage type for ClkSrc
- 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
- (free running), 0xFF: not used
-**/
- UINT8 PcieClkSrcUsage[16];
-
-/** Offset 0x018B - ClkReq-to-ClkSrc mapping
- Number of ClkReq signal assigned to ClkSrc
-**/
- UINT8 PcieClkSrcClkReq[16];
-
-/** Offset 0x019B - PCIE RP Access Control Services Extended Capability
- Enable/Disable PCIE RP Access Control Services Extended Capability
-**/
- UINT8 PcieRpAcsEnabled[24];
-
-/** Offset 0x01B3 - PCIE RP Clock Power Management
- Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
- can still be controlled by L1 PM substates mechanism
-**/
- UINT8 PcieRpEnableCpm[24];
-
-/** Offset 0x01CB - PCIE RP Detect Timeout Ms
- The number of milliseconds within 0~65535 in reference code will wait for link to
- exit Detect state for enabled ports before assuming there is no device and potentially
- disabling the port.
-**/
- UINT16 PcieRpDetectTimeoutMs[24];
-
-/** Offset 0x01FB - ModPHY SUS Power Domain Dynamic Gating
- Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
- PCH-H. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 PmcModPhySusPgEnable;
-
-/** Offset 0x01FC - SlpS0WithGbeSupport
- Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 SlpS0WithGbeSupport;
-
-/** Offset 0x01FD
-**/
- UINT8 UnusedUpdSpace6[3];
-
-/** Offset 0x0200 - Enable/Disable SA CRID
- Enable: SA CRID, Disable (Default): SA CRID
- $EN_DIS
-**/
- UINT8 CridEnable;
-
-/** Offset 0x0201 - DMI ASPM
- 0=Disable, 1:L0s, 2:L1, 3(Default)=L0sL1
- 0:Disable, 1:L0s, 2:L1, 3:L0sL1
-**/
- UINT8 DmiAspm;
-
-/** Offset 0x0202 - PCIe DeEmphasis control per root port
- 0: -6dB, 1(Default): -3.5dB
- 0:-6dB, 1:-3.5dB
-**/
- UINT8 PegDeEmphasis[4];
-
-/** Offset 0x0206 - PCIe Slot Power Limit value per root port
- Slot power limit value per root port
-**/
- UINT8 PegSlotPowerLimitValue[4];
-
-/** Offset 0x020A - PCIe Slot Power Limit scale per root port
- Slot power limit scale per root port
- 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
-**/
- UINT8 PegSlotPowerLimitScale[4];
-
-/** Offset 0x020E - PCIe Physical Slot Number per root port
- Physical Slot Number per root port
-**/
- UINT16 PegPhysicalSlotNumber[4];
-
-/** Offset 0x0216 - Enable/Disable PavpEnable
- Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
- $EN_DIS
-**/
- UINT8 PavpEnable;
-
-/** Offset 0x0217 - CdClock Frequency selection
- 0=337.5 Mhz, 1=450 Mhz, 2=540 Mhz, 3(Default)=675 Mhz
- 0: 337.5 Mhz, 1: 450 Mhz, 2: 540 Mhz, 3: 675 Mhz
-**/
- UINT8 CdClock;
-
-/** Offset 0x0218 - Enable/Disable PeiGraphicsPeimInit
- Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
- $EN_DIS
-**/
- UINT8 PeiGraphicsPeimInit;
-
-/** Offset 0x0219
-**/
- UINT8 UnusedUpdSpace7;
-
-/** Offset 0x021A - Enable or disable GNA device
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 GnaEnable;
-
-/** Offset 0x021B - State of X2APIC_OPT_OUT bit in the DMAR table
- 0=Disable/Clear, 1=Enable/Set
- $EN_DIS
-**/
- UINT8 X2ApicOptOut;
-
-/** Offset 0x021C - Base addresses for VT-d function MMIO access
- Base addresses for VT-d MMIO access per VT-d engine
-**/
- UINT32 VtdBaseAddress[3];
-
-/** Offset 0x0228 - Enable or disable eDP device
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortEdp;
-
-/** Offset 0x0229 - Enable or disable HPD of DDI port B
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortBHpd;
-
-/** Offset 0x022A - Enable or disable HPD of DDI port C
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortCHpd;
-
-/** Offset 0x022B - Enable or disable HPD of DDI port D
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortDHpd;
-
-/** Offset 0x022C - Enable or disable HPD of DDI port F
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortFHpd;
-
-/** Offset 0x022D - Enable or disable DDC of DDI port B
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortBDdc;
-
-/** Offset 0x022E - Enable or disable DDC of DDI port C
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortCDdc;
-
-/** Offset 0x022F - Enable or disable DDC of DDI port D
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 DdiPortDDdc;
-
-/** Offset 0x0230 - Enable or disable DDC of DDI port F
- 0(Default)=Disable, 1=Enable
- $EN_DIS
-**/
- UINT8 DdiPortFDdc;
-
-/** Offset 0x0231 - Enable/Disable SkipS3CdClockInit
- Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
- CD clock in S3 resume due to GOP absent
- $EN_DIS
-**/
- UINT8 SkipS3CdClockInit;
-
-/** Offset 0x0232 - Delta T12 Power Cycle Delay required in ms
- Select the value for delay required. 0(Default)= No delay, 0xFFFF = Auto calculate
- T12 Delay to max 500ms
- 0 : No Delay, 0xFFFF : Auto Calulate T12 Delay
-**/
- UINT16 DeltaT12PowerCycleDelay;
-
-/** Offset 0x0234 - Blt Buffer Address
- Address of Blt buffer
-**/
- UINT32 BltBufferAddress;
-
-/** Offset 0x0238 - Blt Buffer Size
- Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
- EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
-**/
- UINT32 BltBufferSize;
-
-/** Offset 0x023C - SaPostMemProductionRsvd
- Reserved for SA Post-Mem Production
- $EN_DIS
-**/
- UINT8 SaPostMemProductionRsvd[35];
-
-/** Offset 0x025F - PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable
- PCIE RP Disable Gen2PLL Shutdown and L1 Clock Gating Enable Workaround needed for
- Alpine ridge
-**/
- UINT8 PcieRootPortGen2PllL1CgDisable[24];
-
-/** Offset 0x0277 - Advanced Encryption Standard (AES) feature
- Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
- $EN_DIS
-**/
- UINT8 AesEnable;
-
-/** Offset 0x0278 - Power State 3 enable/disable
- PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
- For all VR Indexes
-**/
- UINT8 Psi3Enable[5];
-
-/** Offset 0x027D - Power State 4 enable/disable
- PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
- all VR Indexes
-**/
- UINT8 Psi4Enable[5];
-
-/** Offset 0x0282 - Imon slope correction
- PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
- Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
-**/
- UINT8 ImonSlope[5];
-
-/** Offset 0x0287 - Imon offset correction
- PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
- Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
-**/
- UINT8 ImonOffset[5];
-
-/** Offset 0x028C - Enable/Disable BIOS configuration of VR
- Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
-**/
- UINT8 VrConfigEnable[5];
-
-/** Offset 0x0291 - Thermal Design Current enable/disable
- PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
- Enable.For all VR Indexes
-**/
- UINT8 TdcEnable[5];
-
-/** Offset 0x0296 - HECI3 state
- PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
- Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
- , 8 - 8ms , 10 - 10ms.For all VR Indexe
-**/
- UINT8 TdcTimeWindow[5];
-
-/** Offset 0x029B - Thermal Design Current Lock
- PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
- all VR Indexes
-**/
- UINT8 TdcLock[5];
-
-/** Offset 0x02A0 - Platform Psys slope correction
- PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
- 1/100 increment values. Range is 0-200. 125 = 1.25
-**/
- UINT8 PsysSlope;
-
-/** Offset 0x02A1 - Platform Psys offset correction
- PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
- Range 0-255. Value of 100 = 100/4 = 25 offset
-**/
- UINT8 PsysOffset;
-
-/** Offset 0x02A2 - Acoustic Noise Mitigation feature
- Enable or Disable Acoustic Noise Mitigation feature. This has to be enabled to program
- slew rate configuration for all VR domains, Pre Wake, Ramp Up and, Ramp Down times.<b>0:
- Disabled</b>; 1: Enabled
- $EN_DIS
-**/
- UINT8 AcousticNoiseMitigation;
-
-/** Offset 0x02A3 - Disable Fast Slew Rate for Deep Package C States for VR IA domain
- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
- feature enabled. <b>0: False</b>; 1: True
- $EN_DIS
-**/
- UINT8 FastPkgCRampDisableIa;
-
-/** Offset 0x02A4 - Slew Rate configuration for Deep Package C States for VR IA domain
- Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
-**/
- UINT8 SlowSlewRateForIa;
-
-/** Offset 0x02A5 - Slew Rate configuration for Deep Package C States for VR GT domain
- Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
-**/
- UINT8 SlowSlewRateForGt;
-
-/** Offset 0x02A6 - Slew Rate configuration for Deep Package C States for VR SA domain
- Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
-**/
- UINT8 SlowSlewRateForSa;
-
-/** Offset 0x02A7 - Thermal Design Current current limit
- PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
- Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
-**/
- UINT16 TdcPowerLimit[5];
-
-/** Offset 0x02B1 - AcLoadline
- PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
- 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
-**/
- UINT16 AcLoadline[5];
-
-/** Offset 0x02BB
-**/
- UINT8 UnusedUpdSpace8[10];
-
-/** Offset 0x02C5 - DcLoadline
- PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
- 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
-**/
- UINT16 DcLoadline[5];
-
-/** Offset 0x02CF - Power State 1 Threshold current
- PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
-**/
- UINT16 Psi1Threshold[5];
-
-/** Offset 0x02D9 - Power State 2 Threshold current
- PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
-**/
- UINT16 Psi2Threshold[5];
-
-/** Offset 0x02E3 - Power State 3 Threshold current
- PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
-**/
- UINT16 Psi3Threshold[5];
-
-/** Offset 0x02ED - Icc Max limit
- PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
-**/
- UINT16 IccMax[5];
-
-/** Offset 0x02F7 - VR Voltage Limit
- PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
-**/
- UINT16 VrVoltageLimit[5];
-
-/** Offset 0x0301 - Disable Fast Slew Rate for Deep Package C States for VR GT domain
- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
- feature enabled. <b>0: False</b>; 1: True
- $EN_DIS
-**/
- UINT8 FastPkgCRampDisableGt;
-
-/** Offset 0x0302 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
- feature enabled. <b>0: False</b>; 1: True
- $EN_DIS
-**/
- UINT8 FastPkgCRampDisableSa;
-
-/** Offset 0x0303 - Enable VR specific mailbox command
- VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
- VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
- command sent for PS4 exit issue. 11b - Reserved.
- $EN_DIS
-**/
- UINT8 SendVrMbxCmd;
-
-/** Offset 0x0304 - Reserved
- Reserved
-**/
- UINT8 Reserved2;
-
-/** Offset 0x0305 - Enable or Disable TXT
- Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 TxtEnable;
-
-/** Offset 0x0306
-**/
- UINT8 UnusedUpdSpace9[6];
-
-/** Offset 0x030C - Deprecated DO NOT USE Skip Multi-Processor Initialization
- @deprecated SkipMpInit has been moved to FspmUpd
- $EN_DIS
-**/
- UINT8 SkipMpInit;
-
-/** Offset 0x030D - McIVR RFI Frequency Prefix
- PCODE MMIO Mailbox: McIVR RFI Frequency Adjustment Prefix. <b>0: Plus (+)</b>; 1:
- Minus (-).
-**/
- UINT8 McivrRfiFrequencyPrefix;
-
-/** Offset 0x030E - McIVR RFI Frequency Adjustment
- PCODE MMIO Mailbox: Adjust the RFI frequency relative to the nominal frequency in
- increments of 100KHz. For subtraction, change McivrRfiFrequencyPrefix. <b>0: Auto</b>.
-**/
- UINT8 McivrRfiFrequencyAdjust;
-
-/** Offset 0x030F - FIVR RFI Frequency
- PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
- Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
- 0-1535 (Up to 153.5MHz) for 19MHz clock.
-**/
- UINT16 FivrRfiFrequency;
-
-/** Offset 0x0311 - McIVR RFI Spread Spectrum
- PCODE MMIO Mailbox: McIVR RFI Spread Spectrum. <b>0: 0%</b>; 1: +/- 0.5%; 2: +/-
- 1%; 3: +/- 1.5%; 4: +/- 2%; 5: +/- 3%; 6: +/- 4%; 7: +/- 5%; 8: +/- 6%.
-**/
- UINT8 McivrSpreadSpectrum;
-
-/** Offset 0x0312 - FIVR RFI Spread Spectrum
- PCODE MMIO Mailbox: FIVR RFI Spread Spectrum, in 0.1% increments. <b>0: 0%</b>;
- Range: 0.0% to 10.0% (0-100).
-**/
- UINT8 FivrSpreadSpectrum;
-
-/** Offset 0x0313 - Disable Fast Slew Rate for Deep Package C States for VR FIVR domain
- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
- feature enabled. <b>0: False</b>; 1: True
- $EN_DIS
-**/
- UINT8 FastPkgCRampDisableFivr;
-
-/** Offset 0x0314 - Slew Rate configuration for Deep Package C States for VR FIVR domain
- Slew Rate configuration for Deep Package C States for VR FIVR domain based on Acoustic
- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
-**/
- UINT8 SlowSlewRateForFivr;
-
-/** Offset 0x0315 - CpuBistData
- Pointer CPU BIST Data
-**/
- UINT32 CpuBistData;
-
-/** Offset 0x0319 - Activates VR mailbox command for Intersil VR C-state issues.
- Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
- command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
-**/
- UINT8 IslVrCmd;
-
-/** Offset 0x031A - Imon slope1 correction
- PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
- Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
-**/
- UINT16 ImonSlope1[5];
-
-/** Offset 0x0324 - CPU VR Power Delivery Design
- Used to communicate the power delivery design capability of the board. This value
- is an enum of the available power delivery segments that are defined in the Platform
- Design Guide.
-**/
- UINT32 VrPowerDeliveryDesign;
-
-/** Offset 0x0328 - Pre Wake Randomization time
- PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum pre-wake randomization
- time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.
- Range 0-255 <b>0</b>.
-**/
- UINT8 PreWake;
-
-/** Offset 0x0329 - Ramp Up Randomization time
- PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Up randomization
- time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
- 0-255 <b>0</b>.
-**/
- UINT8 RampUp;
-
-/** Offset 0x032A - Ramp Down Randomization time
- PCODE MMIO Mailbox: Acoustic Migitation Range.Defines the maximum Ramp Down randomization
- time in micro ticks.This can be programmed only if AcousticNoiseMigitation is enabled.Range
- 0-255 <b>0</b>.
-**/
- UINT8 RampDown;
-
-/** Offset 0x032B - CpuMpPpi
- Pointer for CpuMpPpi
-**/
- UINT32 CpuMpPpi;
-
-/** Offset 0x032F - CpuMpHob
- Pointer for CpuMpHob. This is optional data buffer for CpuMpPpi usage.
-**/
- UINT32 CpuMpHob;
-
-/** Offset 0x0333 - Enable or Disable processor debug features
- Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 DebugInterfaceEnable;
-
-/** Offset 0x0334 - ReservedCpuPostMemProduction
- Reserved for CPU Post-Mem Production
- $EN_DIS
-**/
- UINT8 ReservedCpuPostMemProduction[18];
-
-/** Offset 0x0346 - Enable DMI ASPM
- Deprecated.
- $EN_DIS
-**/
- UINT8 PchDmiAspm;
-
-/** Offset 0x0347 - Enable Power Optimizer
- Enable DMI Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 PchPwrOptEnable;
-
-/** Offset 0x0348 - PCH Flash Protection Ranges Write Enble
- Write or erase is blocked by hardware.
-**/
- UINT8 PchWriteProtectionEnable[5];
-
-/** Offset 0x034D - PCH Flash Protection Ranges Read Enble
- Read is blocked by hardware.
-**/
- UINT8 PchReadProtectionEnable[5];
-
-/** Offset 0x0352 - PCH Protect Range Limit
- Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
- limit comparison.
-**/
- UINT16 PchProtectedRangeLimit[5];
-
-/** Offset 0x035C - PCH Protect Range Base
- Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
-**/
- UINT16 PchProtectedRangeBase[5];
-
-/** Offset 0x0366 - Enable Pme
- Enable Azalia wake-on-ring.
- $EN_DIS
-**/
- UINT8 PchHdaPme;
-
-/** Offset 0x0367
-**/
- UINT8 UnusedUpdSpace10;
-
-/** Offset 0x0368 - VC Type
- Virtual Channel Type Select: 0: VC0, 1: VC1.
- 0: VC0, 1: VC1
-**/
- UINT8 PchHdaVcType;
-
-/** Offset 0x0369 - HD Audio Link Frequency
- HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
- 0: 6MHz, 1: 12MHz, 2: 24MHz
-**/
- UINT8 PchHdaLinkFrequency;
-
-/** Offset 0x036A - iDisp-Link Frequency
- iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
- 4: 96MHz, 3: 48MHz
-**/
- UINT8 PchHdaIDispLinkFrequency;
-
-/** Offset 0x036B - iDisp-Link T-mode
- iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
- 0: 2T, 1: 1T
-**/
- UINT8 PchHdaIDispLinkTmode;
-
-/** Offset 0x036C - Universal Audio Architecture compliance for DSP enabled system
- 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
- driver or SST driver supported).
- $EN_DIS
-**/
- UINT8 PchHdaDspUaaCompliance;
-
-/** Offset 0x036D - iDisplay Audio Codec disconnection
- 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
- $EN_DIS
-**/
- UINT8 PchHdaIDispCodecDisconnect;
-
-/** Offset 0x036E - USB LFPS Filter selection
- For each byte bits 2:0 are for p, bits 4:6 are for n. 0h:1.6ns, 1h:2.4ns, 2h:3.2ns,
- 3h:4.0ns, 4h:4.8ns, 5h:5.6ns, 6h:6.4ns.
-**/
- UINT8 PchUsbHsioFilterSel[10];
-
-/** Offset 0x0378
-**/
- UINT8 UnusedUpdSpace11[5];
-
-/** Offset 0x037D - Enable PCH Io Apic Entry 24-119
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIoApicEntry24_119;
-
-/** Offset 0x037E - PCH Io Apic ID
- This member determines IOAPIC ID. Default is 0x02.
-**/
- UINT8 PchIoApicId;
-
-/** Offset 0x037F
-**/
- UINT8 UnusedUpdSpace12;
-
-/** Offset 0x0380 - Enable PCH ISH SPI GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshSpiGpioAssign;
-
-/** Offset 0x0381 - Enable PCH ISH UART0 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshUart0GpioAssign;
-
-/** Offset 0x0382 - Enable PCH ISH UART1 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshUart1GpioAssign;
-
-/** Offset 0x0383 - Enable PCH ISH I2C0 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshI2c0GpioAssign;
-
-/** Offset 0x0384 - Enable PCH ISH I2C1 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshI2c1GpioAssign;
-
-/** Offset 0x0385 - Enable PCH ISH I2C2 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshI2c2GpioAssign;
-
-/** Offset 0x0386 - Enable PCH ISH GP_0 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp0GpioAssign;
-
-/** Offset 0x0387 - Enable PCH ISH GP_1 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp1GpioAssign;
-
-/** Offset 0x0388 - Enable PCH ISH GP_2 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp2GpioAssign;
-
-/** Offset 0x0389 - Enable PCH ISH GP_3 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp3GpioAssign;
-
-/** Offset 0x038A - Enable PCH ISH GP_4 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp4GpioAssign;
-
-/** Offset 0x038B - Enable PCH ISH GP_5 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp5GpioAssign;
-
-/** Offset 0x038C - Enable PCH ISH GP_6 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp6GpioAssign;
-
-/** Offset 0x038D - Enable PCH ISH GP_7 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp7GpioAssign;
-
-/** Offset 0x038E - PCH ISH PDT Unlock Msg
- 0: False; 1: True.
- $EN_DIS
-**/
- UINT8 PchIshPdtUnlock;
-
-/** Offset 0x038F - Enable PCH Lan LTR capabilty of PCH internal LAN
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchLanLtrEnable;
-
-/** Offset 0x0390
-**/
- UINT8 UnusedUpdSpace13[3];
-
-/** Offset 0x0393 - Enable LOCKDOWN BIOS LOCK
- Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
- protection.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosLock;
-
-/** Offset 0x0394 - PCH Compatibility Revision ID
- This member describes whether or not the CRID feature of PCH should be enabled.
- $EN_DIS
-**/
- UINT8 PchCrid;
-
-/** Offset 0x0395 - RTC CMOS MEMORY LOCK
- Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
- and and lower 128-byte bank of RTC RAM.
- $EN_DIS
-**/
- UINT8 PchLockDownRtcMemoryLock;
-
-/** Offset 0x0396 - Enable PCIE RP HotPlug
- Indicate whether the root port is hot plug available.
-**/
- UINT8 PcieRpHotPlug[24];
-
-/** Offset 0x03AE - Enable PCIE RP Pm Sci
- Indicate whether the root port power manager SCI is enabled.
-**/
- UINT8 PcieRpPmSci[24];
-
-/** Offset 0x03C6 - Enable PCIE RP Ext Sync
- Indicate whether the extended synch is enabled.
-**/
- UINT8 PcieRpExtSync[24];
-
-/** Offset 0x03DE - Enable PCIE RP Transmitter Half Swing
- Indicate whether the Transmitter Half Swing is enabled.
-**/
- UINT8 PcieRpTransmitterHalfSwing[24];
-
-/** Offset 0x03F6 - Enable PCIE RP Clk Req Detect
- Probe CLKREQ# signal before enabling CLKREQ# based power management.
-**/
- UINT8 PcieRpClkReqDetect[24];
-
-/** Offset 0x040E - PCIE RP Advanced Error Report
- Indicate whether the Advanced Error Reporting is enabled.
-**/
- UINT8 PcieRpAdvancedErrorReporting[24];
-
-/** Offset 0x0426 - PCIE RP Unsupported Request Report
- Indicate whether the Unsupported Request Report is enabled.
-**/
- UINT8 PcieRpUnsupportedRequestReport[24];
-
-/** Offset 0x043E - PCIE RP Fatal Error Report
- Indicate whether the Fatal Error Report is enabled.
-**/
- UINT8 PcieRpFatalErrorReport[24];
-
-/** Offset 0x0456 - PCIE RP No Fatal Error Report
- Indicate whether the No Fatal Error Report is enabled.
-**/
- UINT8 PcieRpNoFatalErrorReport[24];
-
-/** Offset 0x046E - PCIE RP Correctable Error Report
- Indicate whether the Correctable Error Report is enabled.
-**/
- UINT8 PcieRpCorrectableErrorReport[24];
-
-/** Offset 0x0486 - PCIE RP System Error On Fatal Error
- Indicate whether the System Error on Fatal Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnFatalError[24];
-
-/** Offset 0x049E - PCIE RP System Error On Non Fatal Error
- Indicate whether the System Error on Non Fatal Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnNonFatalError[24];
-
-/** Offset 0x04B6 - PCIE RP System Error On Correctable Error
- Indicate whether the System Error on Correctable Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnCorrectableError[24];
-
-/** Offset 0x04CE - PCIE RP Max Payload
- Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
-**/
- UINT8 PcieRpMaxPayload[24];
-
-/** Offset 0x04E6 - PCH USB3 RX HSIO Tuning parameters
- Bits 7:3 are for Signed Magnatude number added to the CTLE code, Bits 2:0 are for
- controlling the input offset
-**/
- UINT8 PchUsbHsioRxTuningParameters[10];
-
-/** Offset 0x04F0 - PCH USB3 HSIO Rx Tuning Enable
- Mask for enabling tuning of HSIO Rx signals of USB3 ports. Bits: 0 - HsioCtrlAdaptOffsetCfgEnable,
- 1 - HsioFilterSelNEnable, 2 - HsioFilterSelPEnable, 3 - HsioOlfpsCfgPullUpDwnResEnable
-**/
- UINT8 PchUsbHsioRxTuningEnable[10];
-
-/** Offset 0x04FA
-**/
- UINT8 UnusedUpdSpace14[4];
-
-/** Offset 0x04FE - PCIE RP Pcie Speed
- Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
- PCH_PCIE_SPEED).
-**/
- UINT8 PcieRpPcieSpeed[24];
-
-/** Offset 0x0516 - PCIE RP Gen3 Equalization Phase Method
- PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: DEPRECATED, hardware equalization;
- 1: hardware equalization; 4: Fixed Coeficients.
-**/
- UINT8 PcieRpGen3EqPh3Method[24];
-
-/** Offset 0x052E - PCIE RP Physical Slot Number
- Indicates the slot number for the root port. Default is the value as root port index.
-**/
- UINT8 PcieRpPhysicalSlotNumber[24];
-
-/** Offset 0x0546 - PCIE RP Completion Timeout
- The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
-**/
- UINT8 PcieRpCompletionTimeout[24];
-
-/** Offset 0x055E
-**/
- UINT8 UnusedUpdSpace15[106];
-
-/** Offset 0x05C8 - PCIE RP Aspm
- The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
- PchPcieAspmAutoConfig.
-**/
- UINT8 PcieRpAspm[24];
-
-/** Offset 0x05E0 - PCIE RP L1 Substates
- The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
- Default is PchPcieL1SubstatesL1_1_2.
-**/
- UINT8 PcieRpL1Substates[24];
-
-/** Offset 0x05F8 - PCIE RP Ltr Enable
- Latency Tolerance Reporting Mechanism.
-**/
- UINT8 PcieRpLtrEnable[24];
-
-/** Offset 0x0610 - PCIE RP Ltr Config Lock
- 0: Disable; 1: Enable.
-**/
- UINT8 PcieRpLtrConfigLock[24];
-
-/** Offset 0x0628 - PCIE Eq Ph3 Lane Param Cm
- PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
-**/
- UINT8 PcieEqPh3LaneParamCm[24];
-
-/** Offset 0x0640 - PCIE Eq Ph3 Lane Param Cp
- PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
-**/
- UINT8 PcieEqPh3LaneParamCp[24];
-
-/** Offset 0x0658 - PCIE Sw Eq CoeffList Cm
- PCH_PCIE_EQ_PARAM. Coefficient C-1.
-**/
- UINT8 PcieSwEqCoeffListCm[5];
-
-/** Offset 0x065D - PCIE Sw Eq CoeffList Cp
- PCH_PCIE_EQ_PARAM. Coefficient C+1.
-**/
- UINT8 PcieSwEqCoeffListCp[5];
-
-/** Offset 0x0662 - PCIE Disable RootPort Clock Gating
- Describes whether the PCI Express Clock Gating for each root port is enabled by
- platform modules. 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PcieDisableRootPortClockGating;
-
-/** Offset 0x0663 - PCIE Enable Peer Memory Write
- This member describes whether Peer Memory Writes are enabled on the platform.
- $EN_DIS
-**/
- UINT8 PcieEnablePeerMemoryWrite;
-
-/** Offset 0x0664
-**/
- UINT8 UnusedUpdSpace16;
-
-/** Offset 0x0665 - PCIE Compliance Test Mode
- Compliance Test Mode shall be enabled when using Compliance Load Board.
- $EN_DIS
-**/
- UINT8 PcieComplianceTestMode;
-
-/** Offset 0x0666 - PCIE Rp Function Swap
- Allows BIOS to use root port function number swapping when root port of function
- 0 is disabled.
- $EN_DIS
-**/
- UINT8 PcieRpFunctionSwap;
-
-/** Offset 0x0667 - Teton Glacier Support
- Enables support for the Teton Glacier card.
- $EN_DIS
-**/
- UINT8 TetonGlacierSupport;
-
-/** Offset 0x0668 - Teton Glacier Cycle Router
- Specify to which cycle router Teton Glacier is connected, it is valid only when
- Teton Glacier support is enabled. Default is 0 for CNP-H system and 1 for CNP-LP system
-**/
- UINT8 TetonGlacierCR;
-
-/** Offset 0x0669 - PCH Pm PME_B0_S5_DIS
- When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
- $EN_DIS
-**/
- UINT8 PchPmPmeB0S5Dis;
-
-/** Offset 0x066A - SPI ChipSelect signal polarity
- Selects SPI ChipSelect signal polarity.
-**/
- UINT8 SerialIoSpiCsPolarity[3];
-
-/** Offset 0x066D - PCIE IMR
- Enables Isolated Memory Region for PCIe.
- $EN_DIS
-**/
- UINT8 PcieRpImrEnabled;
-
-/** Offset 0x066E - PCIE IMR port number
- Selects PCIE root port number for IMR feature.
-**/
- UINT8 PcieRpImrSelection;
-
-/** Offset 0x066F
-**/
- UINT8 UnusedUpdSpace17;
-
-/** Offset 0x0670 - PCH Pm Wol Enable Override
- Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
- $EN_DIS
-**/
- UINT8 PchPmWolEnableOverride;
-
-/** Offset 0x0671 - PCH Pm Pcie Wake From DeepSx
- Determine if enable PCIe to wake from deep Sx.
- $EN_DIS
-**/
- UINT8 PchPmPcieWakeFromDeepSx;
-
-/** Offset 0x0672 - PCH Pm WoW lan Enable
- Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
- $EN_DIS
-**/
- UINT8 PchPmWoWlanEnable;
-
-/** Offset 0x0673 - PCH Pm WoW lan DeepSx Enable
- Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
- PWRM_CFG3 register.
- $EN_DIS
-**/
- UINT8 PchPmWoWlanDeepSxEnable;
-
-/** Offset 0x0674 - PCH Pm Lan Wake From DeepSx
- Determine if enable LAN to wake from deep Sx.
- $EN_DIS
-**/
- UINT8 PchPmLanWakeFromDeepSx;
-
-/** Offset 0x0675 - PCH Pm Deep Sx Pol
- Deep Sx Policy.
- $EN_DIS
-**/
- UINT8 PchPmDeepSxPol;
-
-/** Offset 0x0676 - PCH Pm Slp S3 Min Assert
- SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
-**/
- UINT8 PchPmSlpS3MinAssert;
-
-/** Offset 0x0677 - PCH Pm Slp S4 Min Assert
- SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
-**/
- UINT8 PchPmSlpS4MinAssert;
-
-/** Offset 0x0678 - PCH Pm Slp Sus Min Assert
- SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
-**/
- UINT8 PchPmSlpSusMinAssert;
-
-/** Offset 0x0679 - PCH Pm Slp A Min Assert
- SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
-**/
- UINT8 PchPmSlpAMinAssert;
-
-/** Offset 0x067A - SLP_S0# Override
- Select 'Auto', it will be auto-configured according to probe type. Select 'Enabled'
- will disable SLP_S0# assertion whereas 'Disabled' will enable SLP_S0# assertion
- when debug is enabled. \n
- Note: This BIOS option should keep 'Auto', other options are intended for advanced
- configuration only.
- 0:Disabled, 1:Enabled, 2:Auto
-**/
- UINT8 SlpS0Override;
-
-/** Offset 0x067B - S0ix Override Settings
- Select 'Auto', it will be auto-configured according to probe type. 'No Change' will
- keep PMC default settings. Or select the desired debug probe type for S0ix Override
- settings.\n
- Reminder: DCI OOB (aka BSSB) uses CCA probe.\n
- Note: This BIOS option should keep 'Auto', other options are intended for advanced
- configuration only.
- 0:No Change, 1:DCI OOB, 2:USB2 DbC, 3:Auto
-**/
- UINT8 SlpS0DisQForDebug;
-
-/** Offset 0x067C - USB Overcurrent Override for DbC
- This option overrides USB Over Current enablement state that USB OC will be disabled
- after enabling this option. Enable when DbC is used to avoid signaling conflicts.
- $EN_DIS
-**/
- UINT8 PchEnableDbcObs;
-
-/** Offset 0x067D
-**/
- UINT8 UnusedUpdSpace18[3];
-
-/** Offset 0x0680 - PCH Pm Lpc Clock Run
- This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
- Default value is Disabled
- $EN_DIS
-**/
- UINT8 PchPmLpcClockRun;
-
-/** Offset 0x0681 - PCH Pm Slp Strch Sus Up
- Enable SLP_X Stretching After SUS Well Power Up.
- $EN_DIS
-**/
- UINT8 PchPmSlpStrchSusUp;
-
-/** Offset 0x0682 - PCH Pm Slp Lan Low Dc
- Enable/Disable SLP_LAN# Low on DC Power.
- $EN_DIS
-**/
- UINT8 PchPmSlpLanLowDc;
-
-/** Offset 0x0683 - PCH Pm Pwr Btn Override Period
- PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
-**/
- UINT8 PchPmPwrBtnOverridePeriod;
-
-/** Offset 0x0684 - PCH Pm Disable Dsx Ac Present Pulldown
- When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
- $EN_DIS
-**/
- UINT8 PchPmDisableDsxAcPresentPulldown;
-
-/** Offset 0x0685
-**/
- UINT8 UnusedUpdSpace19;
-
-/** Offset 0x0686 - PCH Pm Disable Native Power Button
- Power button native mode disable.
- $EN_DIS
-**/
- UINT8 PchPmDisableNativePowerButton;
-
-/** Offset 0x0687 - PCH Pm Slp S0 Enable
- Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
- $EN_DIS
-**/
- UINT8 PchPmSlpS0Enable;
-
-/** Offset 0x0688 - PCH Pm ME_WAKE_STS
- Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
- $EN_DIS
-**/
- UINT8 PchPmMeWakeSts;
-
-/** Offset 0x0689 - PCH Pm WOL_OVR_WK_STS
- Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
- $EN_DIS
-**/
- UINT8 PchPmWolOvrWkSts;
-
-/** Offset 0x068A - PCH Pm Reset Power Cycle Duration
- Could be customized in the unit of second. Please refer to EDS for all support settings.
- 0 is default, 1 is 1 second, 2 is 2 seconds, ...
-**/
- UINT8 PchPmPwrCycDur;
-
-/** Offset 0x068B - PCH Pm Pcie Pll Ssc
- Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
- BIOS override.
-**/
- UINT8 PchPmPciePllSsc;
-
-/** Offset 0x068C
-**/
- UINT8 UnusedUpdSpace20;
-
-/** Offset 0x068D - PCH Sata Pwr Opt Enable
- SATA Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 SataPwrOptEnable;
-
-/** Offset 0x068E - PCH Sata eSATA Speed Limit
- When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
- $EN_DIS
-**/
- UINT8 EsataSpeedLimit;
-
-/** Offset 0x068F - PCH Sata Speed Limit
- Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
-**/
- UINT8 SataSpeedLimit;
-
-/** Offset 0x0690 - Enable SATA Port HotPlug
- Enable SATA Port HotPlug.
-**/
- UINT8 SataPortsHotPlug[8];
-
-/** Offset 0x0698 - Enable SATA Port Interlock Sw
- Enable SATA Port Interlock Sw.
-**/
- UINT8 SataPortsInterlockSw[8];
-
-/** Offset 0x06A0 - Enable SATA Port External
- Enable SATA Port External.
-**/
- UINT8 SataPortsExternal[8];
-
-/** Offset 0x06A8 - Enable SATA Port SpinUp
- Enable the COMRESET initialization Sequence to the device.
-**/
- UINT8 SataPortsSpinUp[8];
-
-/** Offset 0x06B0 - Enable SATA Port Solid State Drive
- 0: HDD; 1: SSD.
-**/
- UINT8 SataPortsSolidStateDrive[8];
-
-/** Offset 0x06B8 - Enable SATA Port Enable Dito Config
- Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
-**/
- UINT8 SataPortsEnableDitoConfig[8];
-
-/** Offset 0x06C0 - Enable SATA Port DmVal
- DITO multiplier. Default is 15.
-**/
- UINT8 SataPortsDmVal[8];
-
-/** Offset 0x06C8 - Enable SATA Port DmVal
- DEVSLP Idle Timeout (DITO), Default is 625.
-**/
- UINT16 SataPortsDitoVal[8];
-
-/** Offset 0x06D8 - Enable SATA Port ZpOdd
- Support zero power ODD.
-**/
- UINT8 SataPortsZpOdd[8];
-
-/** Offset 0x06E0 - PCH Sata Rst Raid Device Id
- Enable RAID Alternate ID.
- 0:Client, 1:Alternate, 2:Server
-**/
- UINT8 SataRstRaidDeviceId;
-
-/** Offset 0x06E1 - PCH Sata Rst Raid0
- RAID0.
- $EN_DIS
-**/
- UINT8 SataRstRaid0;
-
-/** Offset 0x06E2 - PCH Sata Rst Raid1
- RAID1.
- $EN_DIS
-**/
- UINT8 SataRstRaid1;
-
-/** Offset 0x06E3 - PCH Sata Rst Raid10
- RAID10.
- $EN_DIS
-**/
- UINT8 SataRstRaid10;
-
-/** Offset 0x06E4 - PCH Sata Rst Raid5
- RAID5.
- $EN_DIS
-**/
- UINT8 SataRstRaid5;
-
-/** Offset 0x06E5 - PCH Sata Rst Irrt
- Intel Rapid Recovery Technology.
- $EN_DIS
-**/
- UINT8 SataRstIrrt;
-
-/** Offset 0x06E6 - PCH Sata Rst Orom Ui Banner
- OROM UI and BANNER.
- $EN_DIS
-**/
- UINT8 SataRstOromUiBanner;
-
-/** Offset 0x06E7 - PCH Sata Rst Orom Ui Delay
- 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
-**/
- UINT8 SataRstOromUiDelay;
-
-/** Offset 0x06E8 - PCH Sata Rst Hdd Unlock
- Indicates that the HDD password unlock in the OS is enabled.
- $EN_DIS
-**/
- UINT8 SataRstHddUnlock;
-
-/** Offset 0x06E9 - PCH Sata Rst Led Locate
- Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
- enabled on the OS.
- $EN_DIS
-**/
- UINT8 SataRstLedLocate;
-
-/** Offset 0x06EA - PCH Sata Rst Irrt Only
- Allow only IRRT drives to span internal and external ports.
- $EN_DIS
-**/
- UINT8 SataRstIrrtOnly;
-
-/** Offset 0x06EB - PCH Sata Rst Smart Storage
- RST Smart Storage caching Bit.
- $EN_DIS
-**/
- UINT8 SataRstSmartStorage;
-
-/** Offset 0x06EC - PCH Sata Rst Pcie Storage Remap enable
- Enable Intel RST for PCIe Storage remapping.
-**/
- UINT8 SataRstPcieEnable[3];
-
-/** Offset 0x06EF - PCH Sata Rst Pcie Storage Port
- Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
-**/
- UINT8 SataRstPcieStoragePort[3];
-
-/** Offset 0x06F2 - PCH Sata Rst Pcie Device Reset Delay
- PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
-**/
- UINT8 SataRstPcieDeviceResetDelay[3];
-
-/** Offset 0x06F5 - Enable eMMC HS400 Training
- Deprecated.
- $EN_DIS
-**/
- UINT8 PchScsEmmcHs400TuningRequired;
-
-/** Offset 0x06F6 - Set HS400 Tuning Data Valid
- Set if HS400 Tuning Data Valid.
- $EN_DIS
-**/
- UINT8 PchScsEmmcHs400DllDataValid;
-
-/** Offset 0x06F7 - Rx Strobe Delay Control
- Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
-**/
- UINT8 PchScsEmmcHs400RxStrobeDll1;
-
-/** Offset 0x06F8 - Tx Data Delay Control
- Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
-**/
- UINT8 PchScsEmmcHs400TxDataDll;
-
-/** Offset 0x06F9 - I/O Driver Strength
- Deprecated.
- 0:33 Ohm, 1:40 Ohm, 2:50 Ohm
-**/
- UINT8 PchScsEmmcHs400DriverStrength;
-
-/** Offset 0x06FA - PCH SerialIo I2C Pads Termination
- 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
- 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
- pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
- for I2C1, and so on.
-**/
- UINT8 PchSerialIoI2cPadsTermination[6];
-
-/** Offset 0x0700
-**/
- UINT8 UnusedUpdSpace21;
-
-/** Offset 0x0701 - PcdSerialIoUart0PinMuxing
- Select SerialIo Uart0 pin muxing. Setting applicable only if SerialIO UART0 is enabled.
- 0:default pins, 1:pins muxed with CNV_BRI/RGI
-**/
- UINT8 SerialIoUart0PinMuxing;
-
-/** Offset 0x0702
-**/
- UINT8 UnusedUpdSpace22[1];
-
-/** Offset 0x0703 - Enables UART hardware flow control, CTS and RTS lines
- Enables UART hardware flow control, CTS and RTS linesh.
-**/
- UINT8 SerialIoUartHwFlowCtrl[3];
-
-/** Offset 0x0706 - UART Number For Debug Purpose
- UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2. Note: If UART0 is selected
- as CNVi BT Core interface, it cannot be used for debug purpose.
- 0:UART0, 1:UART1, 2:UART2
-**/
- UINT8 SerialIoDebugUartNumber;
-
-/** Offset 0x0707 - Enable Debug UART Controller
- Enable debug UART controller after post.
- $EN_DIS
-**/
- UINT8 SerialIoEnableDebugUartAfterPost;
-
-/** Offset 0x0708 - Enable Serial IRQ
- Determines if enable Serial IRQ.
- $EN_DIS
-**/
- UINT8 PchSirqEnable;
-
-/** Offset 0x0709 - Serial IRQ Mode Select
- Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
- $EN_DIS
-**/
- UINT8 PchSirqMode;
-
-/** Offset 0x070A - Start Frame Pulse Width
- Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
- 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk
-**/
- UINT8 PchStartFramePulse;
-
-/** Offset 0x070B - Reserved
- Reserved
- $EN_DIS
-**/
- UINT8 ReservedForFuture1;
-
-/** Offset 0x070C - Thermal Device SMI Enable
- This locks down SMI Enable on Alert Thermal Sensor Trip.
- $EN_DIS
-**/
- UINT8 PchTsmicLock;
-
-/** Offset 0x070D - Thermal Throttling Custimized T0Level Value
- Custimized T0Level value.
-**/
- UINT16 PchT0Level;
-
-/** Offset 0x070F - Thermal Throttling Custimized T1Level Value
- Custimized T1Level value.
-**/
- UINT16 PchT1Level;
-
-/** Offset 0x0711 - Thermal Throttling Custimized T2Level Value
- Custimized T2Level value.
-**/
- UINT16 PchT2Level;
-
-/** Offset 0x0713 - Enable The Thermal Throttle
- Enable the thermal throttle function.
- $EN_DIS
-**/
- UINT8 PchTTEnable;
-
-/** Offset 0x0714 - PMSync State 13
- When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
- at least T2 state.
- $EN_DIS
-**/
- UINT8 PchTTState13Enable;
-
-/** Offset 0x0715 - Thermal Throttle Lock
- Thermal Throttle Lock.
- $EN_DIS
-**/
- UINT8 PchTTLock;
-
-/** Offset 0x0716 - Thermal Throttling Suggested Setting
- Thermal Throttling Suggested Setting.
- $EN_DIS
-**/
- UINT8 TTSuggestedSetting;
-
-/** Offset 0x0717 - Enable PCH Cross Throttling
- Enable/Disable PCH Cross Throttling
- $EN_DIS
-**/
- UINT8 TTCrossThrottling;
-
-/** Offset 0x0718 - DMI Thermal Sensor Autonomous Width Enable
- DMI Thermal Sensor Autonomous Width Enable.
- $EN_DIS
-**/
- UINT8 PchDmiTsawEn;
-
-/** Offset 0x0719 - DMI Thermal Sensor Suggested Setting
- DMT thermal sensor suggested representative values.
- $EN_DIS
-**/
- UINT8 DmiSuggestedSetting;
-
-/** Offset 0x071A - Thermal Sensor 0 Target Width
- DMT thermal sensor suggested representative values.
- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
-**/
- UINT8 DmiTS0TW;
-
-/** Offset 0x071B - Thermal Sensor 1 Target Width
- Thermal Sensor 1 Target Width.
- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
-**/
- UINT8 DmiTS1TW;
-
-/** Offset 0x071C - Thermal Sensor 2 Target Width
- Thermal Sensor 2 Target Width.
- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
-**/
- UINT8 DmiTS2TW;
-
-/** Offset 0x071D - Thermal Sensor 3 Target Width
- Thermal Sensor 3 Target Width.
- 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
-**/
- UINT8 DmiTS3TW;
-
-/** Offset 0x071E - Port 0 T1 Multipler
- Port 0 T1 Multipler.
-**/
- UINT8 SataP0T1M;
-
-/** Offset 0x071F - Port 0 T2 Multipler
- Port 0 T2 Multipler.
-**/
- UINT8 SataP0T2M;
-
-/** Offset 0x0720 - Port 0 T3 Multipler
- Port 0 T3 Multipler.
-**/
- UINT8 SataP0T3M;
-
-/** Offset 0x0721 - Port 0 Tdispatch
- Port 0 Tdispatch.
-**/
- UINT8 SataP0TDisp;
-
-/** Offset 0x0722 - Port 1 T1 Multipler
- Port 1 T1 Multipler.
-**/
- UINT8 SataP1T1M;
-
-/** Offset 0x0723 - Port 1 T2 Multipler
- Port 1 T2 Multipler.
-**/
- UINT8 SataP1T2M;
-
-/** Offset 0x0724 - Port 1 T3 Multipler
- Port 1 T3 Multipler.
-**/
- UINT8 SataP1T3M;
-
-/** Offset 0x0725 - Port 1 Tdispatch
- Port 1 Tdispatch.
-**/
- UINT8 SataP1TDisp;
-
-/** Offset 0x0726 - Port 0 Tinactive
- Port 0 Tinactive.
-**/
- UINT8 SataP0Tinact;
-
-/** Offset 0x0727 - Port 0 Alternate Fast Init Tdispatch
- Port 0 Alternate Fast Init Tdispatch.
- $EN_DIS
-**/
- UINT8 SataP0TDispFinit;
-
-/** Offset 0x0728 - Port 1 Tinactive
- Port 1 Tinactive.
-**/
- UINT8 SataP1Tinact;
-
-/** Offset 0x0729 - Port 1 Alternate Fast Init Tdispatch
- Port 1 Alternate Fast Init Tdispatch.
- $EN_DIS
-**/
- UINT8 SataP1TDispFinit;
-
-/** Offset 0x072A - Sata Thermal Throttling Suggested Setting
- Sata Thermal Throttling Suggested Setting.
- $EN_DIS
-**/
- UINT8 SataThermalSuggestedSetting;
-
-/** Offset 0x072B - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
- $EN_DIS
-**/
- UINT8 PchMemoryThrottlingEnable;
-
-/** Offset 0x072C - Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryPmsyncEnable[2];
-
-/** Offset 0x072E - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryC0TransmitEnable[2];
-
-/** Offset 0x0730 - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryPinSelection[2];
-
-/** Offset 0x0732 - Thermal Device Temperature
- Decides the temperature.
-**/
- UINT16 PchTemperatureHotLevel;
-
-/** Offset 0x0734 - Enable xHCI Compliance Mode
- Compliance Mode can be enabled for testing through this option but this is disabled
- by default.
- $EN_DIS
-**/
- UINT8 PchEnableComplianceMode;
-
-/** Offset 0x0735 - USB2 Port Over Current Pin
- Describe the specific over current pin number of USB 2.0 Port N.
-**/
- UINT8 Usb2OverCurrentPin[16];
-
-/** Offset 0x0745 - USB3 Port Over Current Pin
- Describe the specific over current pin number of USB 3.0 Port N.
-**/
- UINT8 Usb3OverCurrentPin[10];
-
-/** Offset 0x074F - Enable 8254 Static Clock Gating
- Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
- might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
- boot legacy OS using 8254 timer. Also enable this while S0ix is enabled.
- $EN_DIS
-**/
- UINT8 Enable8254ClockGating;
-
-/** Offset 0x0750 - PCH Sata Rst Optane Memory
- Optane Memory
- $EN_DIS
-**/
- UINT8 SataRstOptaneMemory;
-
-/** Offset 0x0751 - PCH Sata Rst CPU Attached Storage
- CPU Attached Storage
- $EN_DIS
-**/
- UINT8 SataRstCpuAttachedStorage;
-
-/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3
- This is only applicable when Enable8254ClockGating is disabled. FSP will do the
- 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
- avoids the SMI requirement for the programming.
- $EN_DIS
-**/
- UINT8 Enable8254ClockGatingOnS3;
-
-/** Offset 0x0753
-**/
- UINT8 UnusedUpdSpace23;
-
-/** Offset 0x0754 - Pch PCIE device override table pointer
- The PCIe device table is being used to override PCIe device ASPM settings. This
- is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
- refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
- must be 0.
-**/
- UINT32 PchPcieDeviceOverrideTablePtr;
-
-/** Offset 0x0758 - Enable TCO timer.
- When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
- huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
- emulation must be enabled, and WDAT table must not be exposed to the OS.
- $EN_DIS
-**/
- UINT8 EnableTcoTimer;
-
-/** Offset 0x0759 - BgpdtHash[4]
- BgpdtHash values
-**/
- UINT64 BgpdtHash[4];
-
-/** Offset 0x0779 - BiosGuardAttr
- BiosGuardAttr default values
-**/
- UINT32 BiosGuardAttr;
-
-/** Offset 0x077D - BiosGuardModulePtr
- BiosGuardModulePtr default values
-**/
- UINT64 BiosGuardModulePtr;
-
-/** Offset 0x0785 - SendEcCmd
- SendEcCmd function pointer. \n
- @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
- EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
-**/
- UINT64 SendEcCmd;
-
-/** Offset 0x078D - EcCmdProvisionEav
- Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
-**/
- UINT8 EcCmdProvisionEav;
-
-/** Offset 0x078E - EcCmdLock
- EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
-**/
- UINT8 EcCmdLock;
-
-/** Offset 0x078F - SgxEpoch0
- SgxEpoch0 default values
-**/
- UINT64 SgxEpoch0;
-
-/** Offset 0x0797 - SgxEpoch1
- SgxEpoch1 default values
-**/
- UINT64 SgxEpoch1;
-
-/** Offset 0x079F - SgxSinitNvsData
- SgxSinitNvsData default values
-**/
- UINT8 SgxSinitNvsData;
-
-/** Offset 0x07A0 - Si Config CSM Flag.
- Platform specific common policies that used by several silicon components. CSM status flag.
- $EN_DIS
-**/
- UINT8 SiCsmFlag;
-
-/** Offset 0x07A1
-**/
- UINT32 SiSsidTablePtr;
-
-/** Offset 0x07A5
-**/
- UINT16 SiNumberOfSsidTableEntry;
-
-/** Offset 0x07A7 - SATA RST Interrupt Mode
- Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
- 0:Msix, 1:Msi, 2:Legacy
-**/
- UINT8 SataRstInterrupt;
-
-/** Offset 0x07A8 - ME Unconfig on RTC clear
- 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
- 2: Cmos is clear, status unkonwn. 3: Reserved
- 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
- is clear, 3: Reserved
-**/
- UINT8 MeUnconfigOnRtcClear;
-
-/** Offset 0x07A9 - Enable PS_ON.
- PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
- target that will be required by the California Energy Commission (CEC). When FALSE,
- PS_ON is to be disabled.
- $EN_DIS
-**/
- UINT8 PsOnEnable;
-
-/** Offset 0x07AA - Pmc Cpu C10 Gate Pin Enable
- Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
- and VccSTG rails instead of SLP_S0# pin.
- $EN_DIS
-**/
- UINT8 PmcCpuC10GatePinEnable;
-
-/** Offset 0x07AB - Pch Dmi Aspm Ctrl
- ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
- 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
-**/
- UINT8 PchDmiAspmCtrl;
-
-/** Offset 0x07AC
-**/
- UINT8 ReservedFspsUpd[1];
-} FSP_S_CONFIG;
-
-/** Fsp S Test Configuration
-**/
-typedef struct {
-
-/** Offset 0x07AD
-**/
- UINT32 Signature;
-
-/** Offset 0x07B1 - Enable/Disable Device 7
- Enable: Device 7 enabled, Disable (Default): Device 7 disabled
- $EN_DIS
-**/
- UINT8 ChapDeviceEnable;
-
-/** Offset 0x07B2 - Skip PAM register lock
- Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
- PAM registers will be locked by RC
- $EN_DIS
-**/
- UINT8 SkipPamLock;
-
-/** Offset 0x07B3 - EDRAM Test Mode
- Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
- PAM registers will be locked by RC
- 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
-**/
- UINT8 EdramTestMode;
-
-/** Offset 0x07B4 - DMI Extended Sync Control
- Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
- Sync Control
- $EN_DIS
-**/
- UINT8 DmiExtSync;
-
-/** Offset 0x07B5 - DMI IOT Control
- Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
- $EN_DIS
-**/
- UINT8 DmiIot;
-
-/** Offset 0x07B6 - PEG Max Payload size per root port
- 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
- 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
-**/
- UINT8 PegMaxPayload[4];
-
-/** Offset 0x07BA - Enable/Disable IGFX RenderStandby
- Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
- $EN_DIS
-**/
- UINT8 RenderStandby;
-
-/** Offset 0x07BB - Enable/Disable IGFX PmSupport
- Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
- $EN_DIS
-**/
- UINT8 PmSupport;
-
-/** Offset 0x07BC - Enable/Disable CdynmaxClamp
- Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
- $EN_DIS
-**/
- UINT8 CdynmaxClampEnable;
-
-/** Offset 0x07BD - Disable VT-d
- 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
- $EN_DIS
-**/
- UINT8 VtdDisable;
-
-/** Offset 0x07BE - GT Frequency Limit
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
-**/
- UINT8 GtFreqMax;
-
-/** Offset 0x07BF - Disable Turbo GT
- 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
- $EN_DIS
-**/
- UINT8 DisableTurboGt;
-
-/** Offset 0x07C0 - SaPostMemTestRsvd
- Reserved for SA Post-Mem Test
- $EN_DIS
-**/
- UINT8 SaPostMemTestRsvd[11];
-
-/** Offset 0x07CB - 1-Core Ratio Limit
- 1-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 1-Core
- Ratio Limit Must be greater than or equal to 2-Core Ratio Limit, 3-Core Ratio Limit,
- 4-Core Ratio Limit, 5-Core Ratio Limit, 6-Core Ratio Limit, 7-Core Ratio Limit,
- 8-Core Ratio Limit. Range is 0 to 255
-**/
- UINT8 OneCoreRatioLimit;
-
-/** Offset 0x07CC - 2-Core Ratio Limit
- 2-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 2-Core
- Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
-**/
- UINT8 TwoCoreRatioLimit;
-
-/** Offset 0x07CD - 3-Core Ratio Limit
- 3-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 3-Core
- Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
-**/
- UINT8 ThreeCoreRatioLimit;
-
-/** Offset 0x07CE - 4-Core Ratio Limit
- 4-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 4-Core
- Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
-**/
- UINT8 FourCoreRatioLimit;
-
-/** Offset 0x07CF - Enable or Disable HWP
- Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
- 2-3:Reserved
- $EN_DIS
-**/
- UINT8 Hwp;
-
-/** Offset 0x07D0 - Hardware Duty Cycle Control
- Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
- $EN_DIS
-**/
- UINT8 HdcControl;
-
-/** Offset 0x07D1 - Package Long duration turbo mode time
- Package Long duration turbo mode time window in seconds. 0 = AUTO, uses 28 seconds.
- Valid values(Unit in seconds) 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40
- , 48 , 56 , 64 , 80 , 96 , 112 , 128
-**/
- UINT8 PowerLimit1Time;
-
-/** Offset 0x07D2 - Short Duration Turbo Mode
- Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 PowerLimit2;
-
-/** Offset 0x07D3 - Turbo settings Lock
- Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
- $EN_DIS
-**/
- UINT8 TurboPowerLimitLock;
-
-/** Offset 0x07D4 - Package PL3 time window
- Package PL3 time window range for this policy from 0 to 64ms
-**/
- UINT8 PowerLimit3Time;
-
-/** Offset 0x07D5 - Package PL3 Duty Cycle
- Package PL3 Duty Cycle; Valid Range is 0 to 100
-**/
- UINT8 PowerLimit3DutyCycle;
-
-/** Offset 0x07D6 - Package PL3 Lock
- Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
- $EN_DIS
-**/
- UINT8 PowerLimit3Lock;
-
-/** Offset 0x07D7 - Package PL4 Lock
- Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
- $EN_DIS
-**/
- UINT8 PowerLimit4Lock;
-
-/** Offset 0x07D8 - TCC Activation Offset
- TCC Activation Offset. Offset from factory set TCC activation temperature at which
- the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
- Temperature, in volts.For Y SKU, the recommended default for this policy is <b>15</b>,
- For all other SKUs the recommended default are <b>0</b>
-**/
- UINT8 TccActivationOffset;
-
-/** Offset 0x07D9 - Tcc Offset Clamp Enable/Disable
- Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
- below P1.For Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
- For all other SKUs the recommended default are <b>0: Disabled</b>.
- $EN_DIS
-**/
- UINT8 TccOffsetClamp;
-
-/** Offset 0x07DA - Tcc Offset Lock
- Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
- target; <b>0: Disabled</b>; 1: Enabled.
- $EN_DIS
-**/
- UINT8 TccOffsetLock;
-
-/** Offset 0x07DB - Custom Ratio State Entries
- The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
- ratio table.Sets the number of custom P-states. At least 2 states must be present
-**/
- UINT8 NumberOfEntries;
-
-/** Offset 0x07DC - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 1. Valid Range 0
- to 128, 0 = AUTO
-**/
- UINT8 Custom1PowerLimit1Time;
-
-/** Offset 0x07DD - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
-**/
- UINT8 Custom1TurboActivationRatio;
-
-/** Offset 0x07DE - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom1ConfigTdpControl;
-
-/** Offset 0x07DF - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 2. Valid Range 0
- to 128, 0 = AUTO
-**/
- UINT8 Custom2PowerLimit1Time;
-
-/** Offset 0x07E0 - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
-**/
- UINT8 Custom2TurboActivationRatio;
-
-/** Offset 0x07E1 - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom2ConfigTdpControl;
-
-/** Offset 0x07E2 - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 3. Valid Range 0
- to 128, 0 = AUTO
-**/
- UINT8 Custom3PowerLimit1Time;
-
-/** Offset 0x07E3 - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
-**/
- UINT8 Custom3TurboActivationRatio;
-
-/** Offset 0x07E4 - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom3ConfigTdpControl;
-
-/** Offset 0x07E5 - ConfigTdp mode settings Lock
- Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 ConfigTdpLock;
-
-/** Offset 0x07E6 - Load Configurable TDP SSDT
- Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ConfigTdpBios;
-
-/** Offset 0x07E7 - PL1 Enable value
- PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 PsysPowerLimit1;
-
-/** Offset 0x07E8 - PL1 timewindow
- PL1 timewindow in seconds. 0 = AUTO, uses 28 seconds. Valid values(Unit in seconds)
- 1 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
-**/
- UINT8 PsysPowerLimit1Time;
-
-/** Offset 0x07E9 - PL2 Enable Value
- PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
- 1: Enable.
- $EN_DIS
-**/
- UINT8 PsysPowerLimit2;
-
-/** Offset 0x07EA - Enable or Disable MLC Streamer Prefetcher
- Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MlcStreamerPrefetcher;
-
-/** Offset 0x07EB - Enable or Disable MLC Spatial Prefetcher
- Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 MlcSpatialPrefetcher;
-
-/** Offset 0x07EC - Enable or Disable Monitor /MWAIT instructions
- Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MonitorMwaitEnable;
-
-/** Offset 0x07ED - Enable or Disable initialization of machine check registers
- Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MachineCheckEnable;
-
-/** Offset 0x07EE - Deprecated DO NOT USE Enable or Disable processor debug features
- @deprecated Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 DebugInterfaceEnable;
-
-/** Offset 0x07EF - Lock or Unlock debug interface features
- Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 DebugInterfaceLockEnable;
-
-/** Offset 0x07F0 - AP Idle Manner of waiting for SIPI
- AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
- 1: HALT loop, 2: MWAIT loop, 3: RUN loop
-**/
- UINT8 ApIdleManner;
-
-/** Offset 0x07F1 - Control on Processor Trace output scheme
- Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
- 0: Single Range Output, 1: ToPA Output
-**/
- UINT8 ProcessorTraceOutputScheme;
-
-/** Offset 0x07F2 - Enable or Disable Processor Trace feature
- Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ProcessorTraceEnable;
-
-/** Offset 0x07F3 - Base of memory region allocated for Processor Trace
- Base address of memory region allocated for Processor Trace. Processor Trace requires
- 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
-**/
- UINT64 ProcessorTraceMemBase;
-
-/** Offset 0x07FB - Memory region allocation for Processor Trace
- Length in bytes of memory region allocated for Processor Trace. Processor Trace
- requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
-**/
- UINT32 ProcessorTraceMemLength;
-
-/** Offset 0x07FF - Enable or Disable Voltage Optimization feature
- Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 VoltageOptimization;
-
-/** Offset 0x0800 - Enable or Disable Intel SpeedStep Technology
- Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 Eist;
-
-/** Offset 0x0801 - Enable or Disable Energy Efficient P-state
- Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
- <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnergyEfficientPState;
-
-/** Offset 0x0802 - Enable or Disable Energy Efficient Turbo
- Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
- <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnergyEfficientTurbo;
-
-/** Offset 0x0803 - Enable or Disable T states
- Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 TStates;
-
-/** Offset 0x0804 - Enable or Disable Bi-Directional PROCHOT#
- Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 BiProcHot;
-
-/** Offset 0x0805 - Enable or Disable PROCHOT# signal being driven externally
- Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 DisableProcHotOut;
-
-/** Offset 0x0806 - Enable or Disable PROCHOT# Response
- Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ProcHotResponse;
-
-/** Offset 0x0807 - Enable or Disable VR Thermal Alert
- Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 DisableVrThermalAlert;
-
-/** Offset 0x0808 - Enable or Disable Thermal Reporting
- Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 AutoThermalReporting;
-
-/** Offset 0x0809 - Enable or Disable Thermal Monitor
- Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 ThermalMonitor;
-
-/** Offset 0x080A - Enable or Disable CPU power states (C-states)
- Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 Cx;
-
-/** Offset 0x080B - Configure C-State Configuration Lock
- Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 PmgCstCfgCtrlLock;
-
-/** Offset 0x080C - Enable or Disable Enhanced C-states
- Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C1e;
-
-/** Offset 0x080D - Enable or Disable Package Cstate Demotion
- Enable or Disable Package Cstate Demotion. <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 PkgCStateDemotion;
-
-/** Offset 0x080E - Enable or Disable Package Cstate UnDemotion
- Enable or Disable Package Cstate UnDemotion. <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 PkgCStateUnDemotion;
-
-/** Offset 0x080F - Enable or Disable CState-Pre wake
- Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 CStatePreWake;
-
-/** Offset 0x0810 - Enable or Disable TimedMwait Support.
- Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 TimedMwait;
-
-/** Offset 0x0811 - Enable or Disable IO to MWAIT redirection
- Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 CstCfgCtrIoMwaitRedirection;
-
-/** Offset 0x0812 - Set the Max Pkg Cstate
- Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
- C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
- 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
-**/
- UINT8 PkgCStateLimit;
-
-/** Offset 0x0813 - TimeUnit for C-State Latency Control0
- TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl0TimeUnit;
-
-/** Offset 0x0814 - TimeUnit for C-State Latency Control1
- TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl1TimeUnit;
-
-/** Offset 0x0815 - TimeUnit for C-State Latency Control2
- TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl2TimeUnit;
-
-/** Offset 0x0816 - TimeUnit for C-State Latency Control3
- TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl3TimeUnit;
-
-/** Offset 0x0817 - TimeUnit for C-State Latency Control4
- Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl4TimeUnit;
-
-/** Offset 0x0818 - TimeUnit for C-State Latency Control5
- TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl5TimeUnit;
-
-/** Offset 0x0819 - Interrupt Redirection Mode Select
- Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
- PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
-**/
- UINT8 PpmIrmSetting;
-
-/** Offset 0x081A - Lock prochot configuration
- Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 ProcHotLock;
-
-/** Offset 0x081B - Configuration for boot TDP selection
- Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
- Up;0xFF : Deactivate
-**/
- UINT8 ConfigTdpLevel;
-
-/** Offset 0x081C - Race To Halt
- Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
- in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
- through MSR 1FC bit 20)Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 RaceToHalt;
-
-/** Offset 0x081D - Max P-State Ratio
- Max P-State Ratio, Valid Range 0 to 0x7F
-**/
- UINT8 MaxRatio;
-
-/** Offset 0x081E - P-state ratios for custom P-state table
- P-state ratios for custom P-state table. NumberOfEntries has valid range between
- 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
- are configurable. Valid Range of each entry is 0 to 0x7F
-**/
- UINT8 StateRatio[40];
-
-/** Offset 0x0846 - P-state ratios for max 16 version of custom P-state table
- P-state ratios for max 16 version of custom P-state table. This table is used for
- OS versions limited to a max of 16 P-States. If the first entry of this table is
- 0, or if Number of Entries is 16 or less, then this table will be ignored, and
- up to the top 16 values of the StateRatio table will be used instead. Valid Range
- of each entry is 0 to 0x7F
-**/
- UINT8 StateRatioMax16[16];
-
-/** Offset 0x0856 - Platform Power Pmax
- PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
- Range 0-1024 Watts. Value of 800 = 100W
-**/
- UINT16 PsysPmax;
-
-/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0
- Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl0Irtl;
-
-/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1
- Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl1Irtl;
-
-/** Offset 0x085C - Interrupt Response Time Limit of C-State LatencyContol2
- Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl2Irtl;
-
-/** Offset 0x085E - Interrupt Response Time Limit of C-State LatencyContol3
- Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl3Irtl;
-
-/** Offset 0x0860 - Interrupt Response Time Limit of C-State LatencyContol4
- Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl4Irtl;
-
-/** Offset 0x0862 - Interrupt Response Time Limit of C-State LatencyContol5
- Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl5Irtl;
-
-/** Offset 0x0864 - Package Long duration turbo mode power limit
- Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
- Valid Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit1;
-
-/** Offset 0x0868 - Package Short duration turbo mode power limit
- Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit2Power;
-
-/** Offset 0x086C - Package PL3 power limit
- Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit3;
-
-/** Offset 0x0870 - Package PL4 power limit
- Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 1023875 in Step size of 125
-**/
- UINT32 PowerLimit4;
-
-/** Offset 0x0874 - Tcc Offset Time Window for RATL
- Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 1023875 in Step size of 125
-**/
- UINT32 TccOffsetTimeWindowForRatl;
-
-/** Offset 0x0878 - Short term Power Limit value for custom cTDP level 1
- Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom1PowerLimit1;
-
-/** Offset 0x087C - Long term Power Limit value for custom cTDP level 1
- Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom1PowerLimit2;
-
-/** Offset 0x0880 - Short term Power Limit value for custom cTDP level 2
- Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom2PowerLimit1;
-
-/** Offset 0x0884 - Long term Power Limit value for custom cTDP level 2
- Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom2PowerLimit2;
-
-/** Offset 0x0888 - Short term Power Limit value for custom cTDP level 3
- Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom3PowerLimit1;
-
-/** Offset 0x088C - Long term Power Limit value for custom cTDP level 3
- Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom3PowerLimit2;
-
-/** Offset 0x0890 - Platform PL1 power
- Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
- 0 to 4095875 in Step size of 125
-**/
- UINT32 PsysPowerLimit1Power;
-
-/** Offset 0x0894 - Platform PL2 power
- Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
- 0 to 4095875 in Step size of 125
-**/
- UINT32 PsysPowerLimit2Power;
-
-/** Offset 0x0898 - Set Three Strike Counter Disable
- False (default): Three Strike counter will be incremented and True: Prevents Three
- Strike counter from incrementing; <b>0: False</b>; 1: True.
- 0: False, 1: True
-**/
- UINT8 ThreeStrikeCounterDisable;
-
-/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
- Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 HwpInterruptControl;
-
-/** Offset 0x089A - 5-Core Ratio Limit
- 5-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 5-Core
- Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
- 0x0:0xFF
-**/
- UINT8 FiveCoreRatioLimit;
-
-/** Offset 0x089B - 6-Core Ratio Limit
- 6-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 6-Core
- Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
- 0x0:0xFF
-**/
- UINT8 SixCoreRatioLimit;
-
-/** Offset 0x089C - 7-Core Ratio Limit
- 7-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 7-Core
- Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
- 0x0:0xFF
-**/
- UINT8 SevenCoreRatioLimit;
-
-/** Offset 0x089D - 8-Core Ratio Limit
- 8-Core Ratio Limit: LFM to Fused, For overclocking part: LFM to 255. This 8-Core
- Ratio Limit Must be Less than or equal to 1-Core Ratio Limit.Range is 0 to 255
- 0x0:0xFF
-**/
- UINT8 EightCoreRatioLimit;
-
-/** Offset 0x089E - Intel Turbo Boost Max Technology 3.0
- Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
- $EN_DIS
-**/
- UINT8 EnableItbm;
-
-/** Offset 0x089F - Intel Turbo Boost Max Technology 3.0 Driver
- Intel Turbo Boost Max Technology 3.0 Driver <b>0: Disabled</b>; 1: Enabled
- $EN_DIS
-**/
- UINT8 EnableItbmDriver;
-
-/** Offset 0x08A0 - Enable or Disable C1 Cstate Demotion
- Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C1StateAutoDemotion;
-
-/** Offset 0x08A1 - Enable or Disable C1 Cstate UnDemotion
- Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C1StateUnDemotion;
-
-/** Offset 0x08A2 - CpuWakeUpTimer
- Enable long CPU Wakeup Timer. When enabled, the cpu internal wakeup time is increased
- to 180 seconds. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 CpuWakeUpTimer;
-
-/** Offset 0x08A3 - Minimum Ring ratio limit override
- Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
- ratio limit
-**/
- UINT8 MinRingRatioLimit;
-
-/** Offset 0x08A4 - Minimum Ring ratio limit override
- Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
- ratio limit
-**/
- UINT8 MaxRingRatioLimit;
-
-/** Offset 0x08A5 - Enable or Disable C3 Cstate Demotion
- Enable or Disable C3 Cstate Demotion. Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C3StateAutoDemotion;
-
-/** Offset 0x08A6 - Enable or Disable C3 Cstate UnDemotion
- Enable or Disable C3 Cstate UnDemotion. Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C3StateUnDemotion;
-
-/** Offset 0x08A7 - ReservedCpuPostMemTest
- Reserved for CPU Post-Mem Test
- $EN_DIS
-**/
- UINT8 ReservedCpuPostMemTest[19];
-
-/** Offset 0x08BA - SgxSinitDataFromTpm
- SgxSinitDataFromTpm default values
-**/
- UINT8 SgxSinitDataFromTpm;
-
-/** Offset 0x08BB - End of Post message
- Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
- EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
- 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
-**/
- UINT8 EndOfPostMessage;
-
-/** Offset 0x08BC - D0I3 Setting for HECI Disable
- Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
- HECI devices
- $EN_DIS
-**/
- UINT8 DisableD0I3SettingForHeci;
-
-/** Offset 0x08BD - HD Audio Reset Wait Timer
- The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
-**/
- UINT16 PchHdaResetWaitTimer;
-
-/** Offset 0x08BF - Enable LOCKDOWN SMI
- Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
- $EN_DIS
-**/
- UINT8 PchLockDownGlobalSmi;
-
-/** Offset 0x08C0 - Enable LOCKDOWN BIOS Interface
- Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosInterface;
-
-/** Offset 0x08C1 - Unlock all GPIO pads
- Force all GPIO pads to be unlocked for debug purpose.
- $EN_DIS
-**/
- UINT8 PchUnlockGpioPads;
-
-/** Offset 0x08C2 - PCH Unlock SBI access
- Deprecated
- $EN_DIS
-**/
- UINT8 PchSbiUnlock;
-
-/** Offset 0x08C3 - PCH Unlock SideBand access
- The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
- 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
- $EN_DIS
-**/
- UINT8 PchSbAccessUnlock;
-
-/** Offset 0x08C4 - PCIE RP Ltr Max Snoop Latency
- Latency Tolerance Reporting, Max Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxSnoopLatency[24];
-
-/** Offset 0x08F4 - PCIE RP Ltr Max No Snoop Latency
- Latency Tolerance Reporting, Max Non-Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxNoSnoopLatency[24];
-
-/** Offset 0x0924 - PCIE RP Snoop Latency Override Mode
- Latency Tolerance Reporting, Snoop Latency Override Mode.
-**/
- UINT8 PcieRpSnoopLatencyOverrideMode[24];
-
-/** Offset 0x093C - PCIE RP Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Snoop Latency Override Multiplier.
-**/
- UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
-
-/** Offset 0x0954 - PCIE RP Snoop Latency Override Value
- Latency Tolerance Reporting, Snoop Latency Override Value.
-**/
- UINT16 PcieRpSnoopLatencyOverrideValue[24];
-
-/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Mode
- Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
-**/
- UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
-
-/** Offset 0x099C - PCIE RP Non Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
-**/
- UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
-
-/** Offset 0x09B4 - PCIE RP Non Snoop Latency Override Value
- Latency Tolerance Reporting, Non-Snoop Latency Override Value.
-**/
- UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
-
-/** Offset 0x09E4 - PCIE RP Slot Power Limit Scale
- Specifies scale used for slot power limit value. Leave as 0 to set to default.
-**/
- UINT8 PcieRpSlotPowerLimitScale[24];
-
-/** Offset 0x09FC - PCIE RP Slot Power Limit Value
- Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
-**/
- UINT16 PcieRpSlotPowerLimitValue[24];
-
-/** Offset 0x0A2C - PCIE RP Upstream Port Transmiter Preset
- Used during Gen3 Link Equalization. Used for all lanes. Default is 5.
-**/
- UINT8 PcieRpUptp[24];
-
-/** Offset 0x0A44 - PCIE RP Downstream Port Transmiter Preset
- Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
-**/
- UINT8 PcieRpDptp[24];
-
-/** Offset 0x0A5C - PCIE RP Enable Port8xh Decode
- This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
- 1: Enable.
- $EN_DIS
-**/
- UINT8 PcieEnablePort8xhDecode;
-
-/** Offset 0x0A5D - PCIE Port8xh Decode Port Index
- The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
-**/
- UINT8 PchPciePort8xhDecodePortIndex;
-
-/** Offset 0x0A5E - PCH Energy Reporting
- Disable/Enable PCH to CPU energy report feature.
- $EN_DIS
-**/
- UINT8 PchPmDisableEnergyReport;
-
-/** Offset 0x0A5F - PCH Sata Test Mode
- Allow entrance to the PCH SATA test modes.
- $EN_DIS
-**/
- UINT8 SataTestMode;
-
-/** Offset 0x0A60 - PCH USB OverCurrent mapping lock enable
- If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
- that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
- $EN_DIS
-**/
- UINT8 PchXhciOcLock;
-
-/** Offset 0x0A61
-**/
- UINT8 UnusedUpdSpace24[17];
-
-/** Offset 0x0A72 - Skip POSTBOOT SAI
- Deprecated
- $EN_DIS
-**/
- UINT8 SkipPostBootSai;
-
-/** Offset 0x0A73 - Mctp Broadcast Cycle
- Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 MctpBroadcastCycle;
-
-/** Offset 0x0A74
-**/
- UINT8 ReservedFspsTestUpd[12];
-} FSP_S_TEST_CONFIG;
-
-/** Fsp S UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSP_S_CONFIG FspsConfig;
-
-/** Offset 0x07AD
-**/
- FSP_S_TEST_CONFIG FspsTestConfig;
-
-/** Offset 0x0A80
-**/
- UINT16 UpdTerminator;
-} FSPS_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h
deleted file mode 100644
index 90fae70158..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/FsptUpd.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPTUPD_H__
-#define __FSPTUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-/** Fsp T Core UPD
-**/
-typedef struct {
-
-/** Offset 0x0020
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x0024
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0028
-**/
- UINT32 CodeRegionBase;
-
-/** Offset 0x002C
-**/
- UINT32 CodeRegionSize;
-
-/** Offset 0x0030
-**/
- UINT8 Reserved[16];
-} FSPT_CORE_UPD;
-
-/** Fsp T Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - PcdSerialIoUartDebugEnable
- Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
- 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
-**/
- UINT8 PcdSerialIoUartDebugEnable;
-
-/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
- Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
- Core interface, it cannot be used for debug purpose.
- 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
- UINT8 PcdSerialIoUartNumber;
-
-/** Offset 0x0042 - PcdSerialIoUart0PinMuxing - FSPT
- Select SerialIo Uart0 pin muxing. Setting valid only if PcdSerialIoUartNumber is
- set to UART0.
- 0:default pins, 1:pins muxed with CNV_BRI/RGI
-**/
- UINT8 PcdSerialIoUart0PinMuxing;
-
-/** Offset 0x0043
-**/
- UINT8 UnusedUpdSpace0;
-
-/** Offset 0x0044
-**/
- UINT32 PcdSerialIoUartInputClock;
-
-/** Offset 0x0048 - Pci Express Base Address
- Base address to be programmed for Pci Express
-**/
- UINT64 PcdPciExpressBaseAddress;
-
-/** Offset 0x0050 - Pci Express Region Length
- Region Length to be programmed for Pci Express
-**/
- UINT32 PcdPciExpressRegionLength;
-
-/** Offset 0x0054
-**/
- UINT8 ReservedFsptUpd1[44];
-} FSP_T_CONFIG;
-
-/** Fsp T UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPT_CORE_UPD FsptCoreUpd;
-
-/** Offset 0x0040
-**/
- FSP_T_CONFIG FsptConfig;
-
-/** Offset 0x0080
-**/
- UINT16 UpdTerminator;
-} FSPT_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
deleted file mode 100644
index 857555b7ff..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/coffeelake/MemInfoHob.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/** @file
- This file contains definitions required for creation of
- Memory S3 Save data, Memory Info data and Memory Platform
- data hobs.
-
-
- Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available under
- the terms and conditions of the BSD License which accompanies this distribution.
- The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-
-**/
-
-#ifndef _MEM_INFO_HOB_H_
-#define _MEM_INFO_HOB_H_
-
-#include <Uefi/UefiMultiPhase.h>
-#include <Pi/PiBootMode.h>
-#include <Pi/PiHob.h>
-
-#pragma pack (push, 1)
-
-extern EFI_GUID gSiMemoryS3DataGuid;
-extern EFI_GUID gSiMemoryInfoDataGuid;
-extern EFI_GUID gSiMemoryPlatformDataGuid;
-
-#define MAX_NODE 1
-#define MAX_CH 2
-#define MAX_DIMM 2
-
-///
-/// Host reset states from MRC.
-///
-#define WARM_BOOT 2
-
-#define R_MC_CHNL_RANK_PRESENT 0x7C
-#define B_RANK0_PRS BIT0
-#define B_RANK1_PRS BIT1
-#define B_RANK2_PRS BIT4
-#define B_RANK3_PRS BIT5
-
-///
-/// Defines taken from MRC so avoid having to include MrcInterface.h
-///
-
-//
-// Matches MAX_SPD_SAVE define in MRC
-//
-#ifndef MAX_SPD_SAVE
-#define MAX_SPD_SAVE 29
-#endif
-
-//
-// MRC version description.
-//
-typedef struct {
- UINT8 Major; ///< Major version number
- UINT8 Minor; ///< Minor version number
- UINT8 Rev; ///< Revision number
- UINT8 Build; ///< Build number
-} SiMrcVersion;
-
-//
-// Matches MrcChannelSts enum in MRC
-//
-#ifndef CHANNEL_NOT_PRESENT
-#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
-#endif
-#ifndef CHANNEL_DISABLED
-#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
-#endif
-#ifndef CHANNEL_PRESENT
-#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
-#endif
-
-//
-// Matches MrcDimmSts enum in MRC
-//
-#ifndef DIMM_ENABLED
-#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
-#endif
-#ifndef DIMM_DISABLED
-#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
-#endif
-#ifndef DIMM_PRESENT
-#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
-#endif
-#ifndef DIMM_NOT_PRESENT
-#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
-#endif
-
-//
-// Matches MrcBootMode enum in MRC
-//
-#ifndef bmCold
-#define bmCold 0 // Cold boot
-#endif
-#ifndef bmWarm
-#define bmWarm 1 // Warm boot
-#endif
-#ifndef bmS3
-#define bmS3 2 // S3 resume
-#endif
-#ifndef bmFast
-#define bmFast 3 // Fast boot
-#endif
-
-//
-// Matches MrcDdrType enum in MRC
-//
-#ifndef MRC_DDR_TYPE_DDR4
-#define MRC_DDR_TYPE_DDR4 0
-#endif
-#ifndef MRC_DDR_TYPE_DDR3
-#define MRC_DDR_TYPE_DDR3 1
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR3
-#define MRC_DDR_TYPE_LPDDR3 2
-#endif
-#ifndef CPU_CFL//CNL
-#ifndef MRC_DDR_TYPE_LPDDR4
-#define MRC_DDR_TYPE_LPDDR4 3
-#endif
-#else//CFL
-#ifndef MRC_DDR_TYPE_UNKNOWN
-#define MRC_DDR_TYPE_UNKNOWN 3
-#endif
-#endif//CPU_CFL-endif
-
-#define MAX_PROFILE_NUM 4 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
-
-//
-// DIMM timings
-//
-typedef struct {
- UINT32 tCK; ///< Memory cycle time, in femtoseconds.
- UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
- UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
- UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
- UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
- UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
- UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
- UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
- UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
- UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
- UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
- UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
- UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
- UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
- UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
- UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
- UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
- UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
- UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
-} MRC_CH_TIMING;
-
-typedef struct {
- UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
- UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
- UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
- UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
-} MRC_TA_TIMING;
-
-///
-/// Memory SMBIOS & OC Memory Data Hob
-///
-typedef struct {
- UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
- UINT8 DimmId;
- UINT32 DimmCapacity; ///< DIMM size in MBytes.
- UINT16 MfgId;
- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
- UINT8 RankInDimm; ///< The number of ranks in this DIMM.
- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
- UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
-} DIMM_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this channel should be used.
- UINT8 ChannelId;
- UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
- DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
-} CHANNEL_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this controller should be used.
- UINT16 DeviceId; ///< The PCI device id of this memory controller.
- UINT8 RevisionId; ///< The PCI revision id of this memory controller.
- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
- CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
- MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
- MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
- MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
- MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
-} CONTROLLER_INFO;
-
-typedef struct {
- UINT8 Revision;
- UINT16 DataWidth; ///< Data width, in bits, of this memory device
- /** As defined in SMBIOS 3.0 spec
- Section 7.18.2 and Table 75
- **/
- UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
- UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
- UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
- /** As defined in SMBIOS 3.0 spec
- Section 7.17.3 and Table 72
- **/
- UINT8 ErrorCorrectionType;
-
- SiMrcVersion Version;
- BOOLEAN EccSupport;
- UINT8 MemoryProfile;
- UINT32 TotalPhysicalMemorySize;
- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
- UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
- UINT8 Ratio;
- UINT8 RefClk;
- UINT32 VddVoltage[MAX_PROFILE_NUM];
- CONTROLLER_INFO Controller[MAX_NODE];
-} MEMORY_INFO_DATA_HOB;
-
-/**
- Memory Platform Data Hob
-
- <b>Revision 1:</b>
- - Initial version.
- <b>Revision 2:</b>
- - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
-**/
-typedef struct {
- UINT8 Revision;
- UINT8 Reserved[3];
- UINT32 BootMode;
- UINT32 TsegSize;
- UINT32 TsegBase;
- UINT32 PrmrrSize;
- UINT32 PrmrrBase;
- UINT32 GttBase;
- UINT32 MmioSize;
- UINT32 PciEBaseAddress;
-#ifdef CPU_CFL
- UINT32 GdxcIotBase;
- UINT32 GdxcIotSize;
- UINT32 GdxcMotBase;
- UINT32 GdxcMotSize;
-#endif //CPU_CFL
-} MEMORY_PLATFORM_DATA;
-
-typedef struct {
- EFI_HOB_GUID_TYPE EfiHobGuidType;
- MEMORY_PLATFORM_DATA Data;
- UINT8 *Buffer;
-} MEMORY_PLATFORM_DATA_HOB;
-
-#pragma pack (pop)
-
-#endif // _MEM_INFO_HOB_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
deleted file mode 100644
index c8cdc5fd27..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/** @file
- FSP CPU Data Config Block.
-
-@copyright
- Copyright (c) 2016 Intel Corporation. All rights reserved
- This software and associated documentation (if any) is furnished
- under a license and may only be used or copied in accordance
- with the terms of the license. Except as permitted by the
- license, no part of this software or documentation may be
- reproduced, stored in a retrieval system, or transmitted in any
- form or by any means without the express written consent of
- Intel Corporation.
- This file contains an 'Intel Peripheral Driver' and is uniquely
- identified as "Intel Reference Module" and is licensed for Intel
- CPUs and chipsets under the terms of your license agreement with
- Intel or your vendor. This file may be modified by the user, subject
- to additional terms of the license agreement.
-
-@par Specification Reference:
-**/
-#ifndef _CPU_CONFIG_FSP_DATA_H_
-#define _CPU_CONFIG_FSP_DATA_H_
-
-#pragma pack (push,1)
-typedef union {
- struct {
- /**
- Enable or Disable Advanced Encryption Standard (AES) feature.
- For some countries, this should be disabled for legal reasons.
- - 0: Disable
- - <b>1: Enable</b>
- **/
- UINT32 AesEnable : 1;
- /**
- Processor Early Power On Configuration FCLK setting.
- - <b>0: 800 MHz (ULT/ULX)</b>.
- - <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.
- - 2: 400 MHz.
- - 3: Reserved.
- **/
- UINT32 FClkFrequency : 2;
- UINT32 EnableRsr : 1; ///< Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
- /**
- Policies to obtain CPU temperature.
- - <b>0: ACPI thermal management uses EC reported temperature values</b>.
- - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU temperature values.
- - 2: ACPI Thermal Management uses EC reported temperature values and DTS SMM is used to handle Out of Spec condition.
- **/
- UINT32 EnableDts : 2;
- UINT32 SmmbaseSwSmiNumber : 8; ///< Software SMI number for handler to save CPU information in SMRAM.
- /**
- Enable or Disable Virtual Machine Extensions (VMX) feature.
- - 0: Disable
- - <b>1: Enable</b>
- **/
- UINT32 VmxEnable : 1;
- /**
- Enable or Disable Trusted Execution Technology (TXT) feature.
- - 0: Disable
- - <b>1: Enable</b>
- **/
- UINT32 TxtEnable : 1;
- UINT32 SkipMpInit : 1; ///< For Fsp only, Silicon Initialization will skip MP Initialization (including BSP) if enabled. For non-FSP, this should always be 0.
- UINT32 RsvdBits : 15; ///< Reserved for future use
- UINT32 Reserved;
- } Bits;
- UINT32 Uint32[2];
-} CPU_CONFIG_FSP_DATA;
-#pragma pack (pop)
-
-#endif // _CPU_CONFIG_FSP_DATA_H_
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
deleted file mode 100644
index bea3509f65..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/** @file
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPUPD_H__
-#define __FSPUPD_H__
-
-#include <FspEas.h>
-
-#pragma pack(1)
-
-#define FSPT_UPD_SIGNATURE 0x545F4450554C424B /* 'KBLUPD_T' */
-
-#define FSPM_UPD_SIGNATURE 0x4D5F4450554C424B /* 'KBLUPD_M' */
-
-#define FSPS_UPD_SIGNATURE 0x535F4450554C424B /* 'KBLUPD_S' */
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
deleted file mode 100644
index 5d9e0c235d..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
+++ /dev/null
@@ -1,1692 +0,0 @@
-/** @file
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPMUPD_H__
-#define __FSPMUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-#include <MemInfoHob.h>
-
-///
-/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
-///
-typedef struct {
- UINT8 Revision;
- UINT8 Rsvd[3];
- UINT16 MeChipInitCrc;
- UINT16 BiosChipInitCrc;
-} SI_CHIPSET_INIT_INFO;
-
-
-/** Fsp M Configuration
-**/
-typedef struct {
-
-/** Offset 0x0040 - Platform Reserved Memory Size
- The minimum platform memory size required to pass control into DXE
-**/
- UINT64 PlatformMemorySize;
-
-/** Offset 0x0048 - Memory SPD Pointer Channel 0 Dimm 0
- Pointer to SPD data in Memory
-**/
- UINT32 MemorySpdPtr00;
-
-/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 1
- Pointer to SPD data in Memory
-**/
- UINT32 MemorySpdPtr01;
-
-/** Offset 0x0050 - Memory SPD Pointer Channel 1 Dimm 0
- Pointer to SPD data in Memory
-**/
- UINT32 MemorySpdPtr10;
-
-/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 1
- Pointer to SPD data in Memory
-**/
- UINT32 MemorySpdPtr11;
-
-/** Offset 0x0058 - SPD Data Length
- Length of SPD Data
- 0x100:256 Bytes, 0x200:512 Bytes
-**/
- UINT16 MemorySpdDataLen;
-
-/** Offset 0x005A - Dq Byte Map CH0
- Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
-**/
- UINT8 DqByteMapCh0[12];
-
-/** Offset 0x0066 - Dq Byte Map CH1
- Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
-**/
- UINT8 DqByteMapCh1[12];
-
-/** Offset 0x0072 - Dqs Map CPU to DRAM CH 0
- Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
-**/
- UINT8 DqsMapCpu2DramCh0[8];
-
-/** Offset 0x007A - Dqs Map CPU to DRAM CH 1
- Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
-**/
- UINT8 DqsMapCpu2DramCh1[8];
-
-/** Offset 0x0082 - RcompResister settings
- Indicates RcompReister settings: Board-dependent
-**/
- UINT16 RcompResistor[3];
-
-/** Offset 0x0088 - RcompTarget settings
- RcompTarget settings: board-dependent
-**/
- UINT16 RcompTarget[5];
-
-/** Offset 0x0092 - Dqs Pins Interleaved Setting
- Indicates DqPinsInterleaved setting: board-dependent
- $EN_DIS
-**/
- UINT8 DqPinsInterleaved;
-
-/** Offset 0x0093 - VREF_CA
- CA Vref routing: board-dependent
- 0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
- 2:VREF_CA to CH_A and VREF_DQ_B to CH_B
-**/
- UINT8 CaVrefConfig;
-
-/** Offset 0x0094 - Smram Mask
- The SMM Regions AB-SEG and/or H-SEG reserved
- 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
-**/
- UINT8 SmramMask;
-
-/** Offset 0x0095 - MRC Fast Boot
- Enables/Disable the MRC fast path thru the MRC
- $EN_DIS
-**/
- UINT8 MrcFastBoot;
-
-/** Offset 0x0096
-**/
- UINT8 UnusedUpdSpace0[2];
-
-/** Offset 0x0098 - Intel Enhanced Debug
- Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
- 0 : Disable, 0x400000 : Enable
-**/
- UINT32 IedSize;
-
-/** Offset 0x009C - Tseg Size
- Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
- 0x0400000:4MB, 0x01000000:16MB
-**/
- UINT32 TsegSize;
-
-/** Offset 0x00A0 - MMIO Size
- Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
-**/
- UINT16 MmioSize;
-
-/** Offset 0x00A2 - Probeless Trace
- Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
- This also requires IED to be enabled.
- $EN_DIS
-**/
- UINT8 ProbelessTrace;
-
-/** Offset 0x00A3
-**/
- UINT8 UnusedUpdSpace1[2];
-
-/** Offset 0x00A5 - Enable SMBus
- Enable/disable SMBus controller.
- $EN_DIS
-**/
- UINT8 SmbusEnable;
-
-/** Offset 0x00A6 - Enable Trace Hub
- Enable/disable Trace Hub function.
- $EN_DIS
-**/
- UINT8 EnableTraceHub;
-
-/** Offset 0x00A7
-**/
- UINT8 UnusedUpdSpace2[60];
-
-/** Offset 0x00E3 - Internal Graphics Pre-allocated Memory
- Size of memory preallocated for internal graphics.
- 0x00:0 MB, 0x01:32 MB, 0x02:64 MB
-**/
- UINT8 IgdDvmt50PreAlloc;
-
-/** Offset 0x00E4 - Internal Graphics
- Enable/disable internal graphics.
- $EN_DIS
-**/
- UINT8 InternalGfx;
-
-/** Offset 0x00E5 - Aperture Size
- Select the Aperture Size.
- 0:128 MB, 1:256 MB, 2:512 MB
-**/
- UINT8 ApertureSize;
-
-/** Offset 0x00E6 - SA GV
- System Agent dynamic frequency support and when enabled memory will be training
- at two different frequencies. Only effects ULX/ULT CPUs. 0=Disabled, 1=FixedLow,
- 2=FixedHigh, and 3=Enabled.
- 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled
-**/
- UINT8 SaGv;
-
-/** Offset 0x00E7 - Rank Margin Tool
- Enable/disable Rank Margin Tool.
- $EN_DIS
-**/
- UINT8 RMT;
-
-/** Offset 0x00E8 - DDR Frequency Limit
- Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
- 2133, 2400 and 0 for Auto.
- 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 0:Auto
-**/
- UINT16 DdrFreqLimit;
-
-/** Offset 0x00EA - Board Type
- MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
- Halo, 7=UP Server
- 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
-**/
- UINT8 UserBd;
-
-/** Offset 0x00EB
-**/
- UINT8 UnusedUpdSpace3[105];
-
-/** Offset 0x0154 - MMA Test Content Pointer
- Pointer to MMA Test Content in Memory
-**/
- UINT32 MmaTestContentPtr;
-
-/** Offset 0x0158 - MMA Test Content Size
- Size of MMA Test Content in Memory
-**/
- UINT32 MmaTestContentSize;
-
-/** Offset 0x015C - MMA Test Config Pointer
- Pointer to MMA Test Config in Memory
-**/
- UINT32 MmaTestConfigPtr;
-
-/** Offset 0x0160 - MMA Test Config Size
- Size of MMA Test Config in Memory
-**/
- UINT32 MmaTestConfigSize;
-
-/** Offset 0x0164
-**/
- UINT8 UnusedUpdSpace4[19];
-
-/** Offset 0x0177 - SPD Profile Selected
- Select DIMM timing profile. Options are 0=Default profile, 1=Custom profile, 2=XMP
- Profile 1, 3=XMP Profile 2
- 0:Default profile, 1:Custom profile, 2:XMP profile 1, 3:XMP profile 2
-**/
- UINT8 SpdProfileSelected;
-
-/** Offset 0x0178 - Memory Voltage
- Memory Voltage Override (Vddq). Default = no override
- 0:Default, 1100:1.10 Volts, 1150:1.15 Volts, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30
- Volts, 1350:1.35 Volts, 1400:1.40 Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55
- Volts, 1600:1.60 Volts, 1650:1.65 Volts
-**/
- UINT16 VddVoltage;
-
-/** Offset 0x017A - Memory Reference Clock
- Automatic, 100MHz, 133MHz.
- 0:Auto, 1:133MHz, 2:100MHz
-**/
- UINT8 RefClk;
-
-/** Offset 0x017B - Memory Ratio
- Automatic or the frequency will equal ratio times reference clock. Set to Auto to
- recalculate memory timings listed below.
- 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
-**/
- UINT8 Ratio;
-
-/** Offset 0x017C - QCLK Odd Ratio
- Adds 133 or 100 MHz to QCLK frequency, depending on RefClk
- $EN_DIS
-**/
- UINT8 OddRatioMode;
-
-/** Offset 0x017D - tCL
- CAS Latency, 0: AUTO, max: 31
-**/
- UINT8 tCL;
-
-/** Offset 0x017E - tFAW
- Min Four Activate Window Delay Time, 0: AUTO, max: 63
-**/
- UINT16 tFAW;
-
-/** Offset 0x0180 - tRAS
- RAS Active Time, 0: AUTO, max: 64
-**/
- UINT16 tRAS;
-
-/** Offset 0x0182 - tCWL
- Min CAS Write Latency Delay Time, 0: AUTO, max: 20
-**/
- UINT8 tCWL;
-
-/** Offset 0x0183 - tRCD/tRP
- RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63
-**/
- UINT8 tRCDtRP;
-
-/** Offset 0x0184 - tREFI
- Refresh Interval, 0: AUTO, max: 65535
-**/
- UINT16 tREFI;
-
-/** Offset 0x0186 - tRFC
- Min Refresh Recovery Delay Time, 0: AUTO, max: 1023
-**/
- UINT16 tRFC;
-
-/** Offset 0x0188 - tRRD
- Min Row Active to Row Active Delay Time, 0: AUTO, max: 15
-**/
- UINT8 tRRD;
-
-/** Offset 0x0189 - tRTP
- Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
- values: 5, 6, 7, 8, 9, 10, 12
-**/
- UINT8 tRTP;
-
-/** Offset 0x018A - tWR
- Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24
- 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24
-**/
- UINT8 tWR;
-
-/** Offset 0x018B - tWTR
- Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28
-**/
- UINT8 tWTR;
-
-/** Offset 0x018C - NMode
- System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
-**/
- UINT8 NModeSupport;
-
-/** Offset 0x018D - DllBwEn[0]
- DllBwEn[0], for 1067 (0..7)
-**/
- UINT8 DllBwEn0;
-
-/** Offset 0x018E - DllBwEn[1]
- DllBwEn[1], for 1333 (0..7)
-**/
- UINT8 DllBwEn1;
-
-/** Offset 0x018F - DllBwEn[2]
- DllBwEn[2], for 1600 (0..7)
-**/
- UINT8 DllBwEn2;
-
-/** Offset 0x0190 - DllBwEn[3]
- DllBwEn[3], for 1867 and up (0..7)
-**/
- UINT8 DllBwEn3;
-
-/** Offset 0x0191 - Command Tristate Support
- Enable/Disable Command Tristate; <b>0: Enable</b>; 1: Disable.
- $EN_DIS
-**/
- UINT8 CmdTriStateDis;
-
-/** Offset 0x0192
-**/
- UINT8 UnusedUpdSpace5[14];
-
-/** Offset 0x01A0 - HECI1 BAR address
- BAR address of HECI1
-**/
- UINT32 Heci1BarAddress;
-
-/** Offset 0x01A4 - HECI2 BAR address
- BAR address of HECI2
-**/
- UINT32 Heci2BarAddress;
-
-/** Offset 0x01A8 - HECI3 BAR address
- BAR address of HECI3
-**/
- UINT32 Heci3BarAddress;
-
-/** Offset 0x01AC - HECI Timeouts
- Enable/Disable. 0: Disable, disable timeout check for HECI, 1: enable
- $EN_DIS
-**/
- UINT8 HeciTimeouts;
-
-/** Offset 0x01AD
-**/
- UINT8 UnusedUpdSpace6[115];
-
-/** Offset 0x0220 - SG dGPU Power Delay
- SG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
- 300=300 microseconds
-**/
- UINT16 SgDelayAfterPwrEn;
-
-/** Offset 0x0222 - SG dGPU Reset Delay
- SG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
- microseconds
-**/
- UINT16 SgDelayAfterHoldReset;
-
-/** Offset 0x0224 - MMIO size adjustment for AUTO mode
- Positive number means increasing MMIO size, Negative value means decreasing MMIO
- size: 0 (Default)=no change to AUTO mode MMIO size
-**/
- UINT16 MmioSizeAdjustment;
-
-/** Offset 0x0226 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
- Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
- Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
- $EN_DIS
-**/
- UINT8 DmiGen3ProgramStaticEq;
-
-/** Offset 0x0227 - Enable/Disable PEG 0
- Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
- it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
- 0:Disable, 1:Enable, 2:AUTO
-**/
- UINT8 Peg0Enable;
-
-/** Offset 0x0228 - Enable/Disable PEG 1
- Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
- it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
- 0:Disable, 1:Enable, 2:AUTO
-**/
- UINT8 Peg1Enable;
-
-/** Offset 0x0229 - Enable/Disable PEG 2
- Disabled(0x0): Disable PEG Port, Enabled(0x1): Enable PEG Port (If Silicon SKU permits
- it), Auto(0x2)(Default): If an endpoint is present, enable the PEG Port, Disable otherwise
- 0:Disable, 1:Enable, 2:AUTO
-**/
- UINT8 Peg2Enable;
-
-/** Offset 0x022A - PEG 0 Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 Peg0MaxLinkSpeed;
-
-/** Offset 0x022B - PEG 1 Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 Peg1MaxLinkSpeed;
-
-/** Offset 0x022C - PEG 2 Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 Peg2MaxLinkSpeed;
-
-/** Offset 0x022D - PEG 0 Max Link Width
- Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
- Limit Link to x2, (0x3):Limit Link to x4, (0x4): Limit Link to x8
- 0:Auto, 1:x1, 2:x2, 3:x4, 4:x8
-**/
- UINT8 Peg0MaxLinkWidth;
-
-/** Offset 0x022E - PEG 1 Max Link Width
- Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
- Limit Link to x2, (0x3):Limit Link to x4
- 0:Auto, 1:x1, 2:x2, 3:x4
-**/
- UINT8 Peg1MaxLinkWidth;
-
-/** Offset 0x022F - PEG 2 Max Link Width
- Auto (Default)(0x0): Maximum possible link width, (0x1): Limit Link to x1, (0x2):
- Limit Link to x2
- 0:Auto, 1:x1, 2:x2
-**/
- UINT8 Peg2MaxLinkWidth;
-
-/** Offset 0x0230 - Power down unused lanes on PEG 0
- (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
- on the max possible link width
- 0:No power saving, 1:Auto
-**/
- UINT8 Peg0PowerDownUnusedLanes;
-
-/** Offset 0x0231 - Power down unused lanes on PEG 1
- (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
- on the max possible link width
- 0:No power saving, 1:Auto
-**/
- UINT8 Peg1PowerDownUnusedLanes;
-
-/** Offset 0x0232 - Power down unused lanes on PEG 2
- (0x0): Do not power down any lane, (0x1): Bios will power down unused lanes based
- on the max possible link width
- 0:No power saving, 1:Auto
-**/
- UINT8 Peg2PowerDownUnusedLanes;
-
-/** Offset 0x0233 - PCIe ASPM programming will happen in relation to the Oprom
- Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
- Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
- Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
- 0:Before, 1:After
-**/
- UINT8 InitPcieAspmAfterOprom;
-
-/** Offset 0x0234 - PCIe Disable Spread Spectrum Clocking
- PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled,
- Disable SSC(0X1) - Disable SSC per platform design or for compliance testing
- 0:Normal Operation, 1:Disable SSC
-**/
- UINT8 PegDisableSpreadSpectrumClocking;
-
-/** Offset 0x0235 - DMI Gen3 Root port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane
-**/
- UINT8 DmiGen3RootPortPreset[4];
-
-/** Offset 0x0239 - DMI Gen3 End port preset values per lane
- Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
-**/
- UINT8 DmiGen3EndPointPreset[4];
-
-/** Offset 0x023D - DMI Gen3 End port Hint values per lane
- Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
-**/
- UINT8 DmiGen3EndPointHint[4];
-
-/** Offset 0x0241 - DMI Gen3 RxCTLEp per-Bundle control
- Range: 0-15, 3 is default for each bundle, must be specified based upon platform design
-**/
- UINT8 DmiGen3RxCtlePeaking[2];
-
-/** Offset 0x0243 - DeEmphasis control for DMI
- DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
- 0: -6dB, 1: -3.5dB
-**/
- UINT8 DmiDeEmphasis;
-
-/** Offset 0x0244 - PEG Gen3 RxCTLEp per-Bundle control
- Range: 0-15, 12 is default for each bundle, must be specified based upon platform design
-**/
- UINT8 PegGen3RxCtlePeaking[8];
-
-/** Offset 0x024C - Memory data pointer for saved preset search results
- The reference code will store the Gen3 Preset Search results in the SaDataHob's
- PegData structure (SA_PEG_DATA) and platform code can save/restore this data to
- skip preset search in the following boots. Range: 0-0xFFFFFFFF, default is 0
-**/
- UINT32 PegDataPtr;
-
-/** Offset 0x0250 - PEG PERST# GPIO information
- The reference code will use the information in this structure in order to reset
- PCIe Gen3 devices during equalization, if necessary
-**/
- UINT8 PegGpioData[16];
-
-/** Offset 0x0260
-**/
- UINT8 UnusedUpdSpace7[1];
-
-/** Offset 0x0261 - PCIe Hot Plug Enable/Disable per port
- 0(Default): Disable, 1: Enable
-**/
- UINT8 PegRootPortHPE[3];
-
-/** Offset 0x0264 - Temporary MMIO address for GTTMMADR
- The reference code will use the information in this structure in order to reset
- PCIe Gen3 devices during equalization, if necessary
-**/
- UINT32 GttMmAdr;
-
-/** Offset 0x0268 - Selection of iGFX GTT Memory size
- 1=2MB, 2=4MB, 3=8MB, Default is 3
- 1:2MB, 2:4MB, 3:8MB
-**/
- UINT16 GttSize;
-
-/** Offset 0x026A - Selection of the primary display device
- 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Switchable Graphics
- 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Switchable Graphics
-**/
- UINT8 PrimaryDisplay;
-
-/** Offset 0x026B - Switchable Graphics GPIO information for PEG 0
- Switchable Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs
-**/
- UINT8 SaRtd3Pcie0Gpio[24];
-
-/** Offset 0x0283 - Switchable Graphics GPIO information for PEG 1
- Switchable Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs
-**/
- UINT8 SaRtd3Pcie1Gpio[24];
-
-/** Offset 0x029B - Switchable Graphics GPIO information for PEG 2
- Switchable Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs
-**/
- UINT8 SaRtd3Pcie2Gpio[24];
-
-/** Offset 0x02B3 - PEG root port Device number for Switchable Graphics dGPU
- Device number to indicate which PEG root port has dGPU
-**/
- UINT8 RootPortDev;
-
-/** Offset 0x02B4 - PEG root port Function number for Switchable Graphics dGPU
- Function number to indicate which PEG root port has dGPU
-**/
- UINT8 RootPortFun;
-
-/** Offset 0x02B5 - Enable/Disable MRC TXT dependency
- When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
- MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
- $EN_DIS
-**/
- UINT8 TxtImplemented;
-
-/** Offset 0x02B6 - Enable/Disable SA OcSupport
- Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
- $EN_DIS
-**/
- UINT8 SaOcSupport;
-
-/** Offset 0x02B7 - GT slice Voltage Mode
- 0(Default): Adaptive, 1: Override
- 0: Adaptive, 1: Override
-**/
- UINT8 GtsVoltageMode;
-
-/** Offset 0x02B8 - GT unslice Voltage Mode
- 0(Default): Adaptive, 1: Override
- 0: Adaptive, 1: Override
-**/
- UINT8 GtusVoltageMode;
-
-/** Offset 0x02B9 - Maximum GTs turbo ratio override
- 0(Default)=Minimal/Auto, 60=Maximum
-**/
- UINT8 GtsMaxOcRatio;
-
-/** Offset 0x02BA - The voltage offset applied to GT slice
- 0(Default)=Minimal, 1000=Maximum
-**/
- UINT16 GtsVoltageOffset;
-
-/** Offset 0x02BC - The GT slice voltage override which is applied to the entire range of GT frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtsVoltageOverride;
-
-/** Offset 0x02BE - adaptive voltage applied during turbo frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtsExtraTurboVoltage;
-
-/** Offset 0x02C0 - voltage offset applied to GT unslice
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtusVoltageOffset;
-
-/** Offset 0x02C2 - GT unslice voltage override which is applied to the entire range of GT frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtusVoltageOverride;
-
-/** Offset 0x02C4 - adaptive voltage applied during turbo frequencies
- 0(Default)=Minimal, 2000=Maximum
-**/
- UINT16 GtusExtraTurboVoltage;
-
-/** Offset 0x02C6 - voltage offset applied to the SA
- 0(Default)=Minimal, 1000=Maximum
-**/
- UINT16 SaVoltageOffset;
-
-/** Offset 0x02C8 - EDRAM ratio override
- EdramRatio is deprecated on Kabylake
-**/
- UINT8 EdramRatio;
-
-/** Offset 0x02C9 - Maximum GTus turbo ratio override
- 0(Default)=Minimal, 60=Maximum
-**/
- UINT8 GtusMaxOcRatio;
-
-/** Offset 0x02CA - BIST on Reset
- Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 BistOnReset;
-
-/** Offset 0x02CB - Skip Stop PBET Timer Enable/Disable
- Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 SkipStopPbet;
-
-/** Offset 0x02CC - C6DRAM power gating feature
- This feature is not supported. BIOS is required to disable. <b>0: Disable</b>
- $EN_DIS
-**/
- UINT8 EnableC6Dram;
-
-/** Offset 0x02CD - Over clocking support
- Over clocking support; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 OcSupport;
-
-/** Offset 0x02CE - Over clocking Lock
- Over clocking Lock Enable/Disable; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 OcLock;
-
-/** Offset 0x02CF - Maximum Core Turbo Ratio Override
- Maximum core turbo ratio override allows to increase CPU core frequency beyond the
- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
-**/
- UINT8 CoreMaxOcRatio;
-
-/** Offset 0x02D0 - Core voltage mode
- Core voltage mode; <b>0: Adaptive</b>; 1: Override.
- $EN_DIS
-**/
- UINT8 CoreVoltageMode;
-
-/** Offset 0x02D1 - Minimum clr turbo ratio override
- Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83
-**/
- UINT8 RingMinOcRatio;
-
-/** Offset 0x02D2 - Maximum clr turbo ratio override
- Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
- fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-83
-**/
- UINT8 RingMaxOcRatio;
-
-/** Offset 0x02D3 - Hyper Threading Enable/Disable
- Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 HyperThreading;
-
-/** Offset 0x02D4 - Enable or Disable CPU Ratio Override
- Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. @note If disabled,
- BIOS will use the default max non-turbo ratio, and will not use any flex ratio setting.
- $EN_DIS
-**/
- UINT8 CpuRatioOverride;
-
-/** Offset 0x02D5 - CPU ratio value
- CPU ratio value. Valid Range 0 to 63
-**/
- UINT8 CpuRatio;
-
-/** Offset 0x02D6 - Boot frequency
- Sets the boot frequency starting from reset vector.- 0: Maximum battery performance.-
- <b>1: Maximum non-turbo performance</b>.- 2: Turbo performance. @note If Turbo
- is selected BIOS will start in max non-turbo mode and switch to Turbo mode.
- 0:0, 1:1, 2:2
-**/
- UINT8 BootFrequency;
-
-/** Offset 0x02D7 - Number of active cores
- Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
- 2 </b>;<b>3: 3 </b>
- 0:All, 1:1, 2:2, 3:3
-**/
- UINT8 ActiveCoreCount;
-
-/** Offset 0x02D8 - Processor Early Power On Configuration FCLK setting
- <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
- 2: 400 MHz. - 3: Reserved
- 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
-**/
- UINT8 FClkFrequency;
-
-/** Offset 0x02D9 - Power JTAG in C10 and deeper power states
- Power JTAG in C10 and deeper power states; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 JtagC10PowerGateDisable;
-
-/** Offset 0x02DA - Enable or Disable VMX
- Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 VmxEnable;
-
-/** Offset 0x02DB - AVX2 Ratio Offset
- 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
- vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
-**/
- UINT8 Avx2RatioOffset;
-
-/** Offset 0x02DC - core voltage override
- The core voltage override which is applied to the entire range of cpu core frequencies.
- Valid Range 0 to 2000
-**/
- UINT16 CoreVoltageOverride;
-
-/** Offset 0x02DE - Core Turbo voltage Adaptive
- Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
- Valid Range 0 to 2000
-**/
- UINT16 CoreVoltageAdaptive;
-
-/** Offset 0x02E0 - Core Turbo voltage Offset
- The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
-**/
- UINT16 CoreVoltageOffset;
-
-/** Offset 0x02E2 - Core PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
-**/
- UINT8 CorePllVoltageOffset;
-
-/** Offset 0x02E3 - Ring Downbin
- Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
- lower than the core ratio. 0: Disable; <b>1: Enable.</b>
- $EN_DIS
-**/
- UINT8 RingDownBin;
-
-/** Offset 0x02E4 - BCLK Adaptive Voltage Enable
- When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
- Disable;<b> 1: Enable
- $EN_DIS
-**/
- UINT8 BclkAdaptiveVoltage;
-
-/** Offset 0x02E5 - BiosGuard
- Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
- $EN_DIS
-**/
- UINT8 BiosGuard;
-
-/** Offset 0x02E6 - EnableSgx
- Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable
- $EN_DIS
-**/
- UINT8 EnableSgx;
-
-/** Offset 0x02E7 - Txt
- Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
- $EN_DIS
-**/
- UINT8 Txt;
-
-/** Offset 0x02E8 - PrmrrSize
- Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
-**/
- UINT32 PrmrrSize;
-
-/** Offset 0x02EC - SinitMemorySize
- Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
-**/
- UINT32 SinitMemorySize;
-
-/** Offset 0x02F0 - TxtDprMemoryBase
- Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
-**/
- UINT64 TxtDprMemoryBase;
-
-/** Offset 0x02F8 - TxtDprMemorySize
- Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable
-**/
- UINT32 TxtDprMemorySize;
-
-/** Offset 0x02FC - TxtHeapMemorySize
- Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
-**/
- UINT32 TxtHeapMemorySize;
-
-/** Offset 0x0300 - FlashWearOutProtection
- Enable/Disable. 0: Disable, Enable/Disable FlashWearOutProtection feature, 1: enable
- $EN_DIS
-**/
- UINT8 FlashWearOutProtection;
-
-/** Offset 0x0301 - ReservedSecurityPreMem
- Reserved for Security Pre-Mem
- $EN_DIS
-**/
- UINT8 ReservedSecurityPreMem[9];
-
-/** Offset 0x030A - PCH HPET Enabled
- Enable/disable PCH HPET.
- $EN_DIS
-**/
- UINT8 PchHpetEnable;
-
-/** Offset 0x030B - PCH HPET BDF valid
- Whether the BDF value is valid. 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchHpetBdfValid;
-
-/** Offset 0x030C - The HPET Base Address
- The HPET base address. Default is 0xFED00000.
-**/
- UINT32 PchHpetBase;
-
-/** Offset 0x0310 - PCH HPET Bus Number
- Bus Number HPETn used as Requestor / Completer ID. Default is 0xF0.
-**/
- UINT8 PchHpetBusNumber;
-
-/** Offset 0x0311 - PCH HPET Device Number
- Device Number HPETn used as Requestor / Completer ID. Default is 0x1F.
-**/
- UINT8 PchHpetDeviceNumber;
-
-/** Offset 0x0312 - PCH HPET Function Number
- Function Number HPETn used as Requestor / Completer ID. Default is 0x00.
-**/
- UINT8 PchHpetFunctionNumber;
-
-/** Offset 0x0313 - Enable PCH HSIO PCIE Rx Set Ctle
- Enable PCH PCIe Gen 3 Set CTLE Value.
-**/
- UINT8 PchPcieHsioRxSetCtleEnable[24];
-
-/** Offset 0x032B - PCH HSIO PCIE Rx Set Ctle Value
- PCH PCIe Gen 3 Set CTLE Value.
-**/
- UINT8 PchPcieHsioRxSetCtle[24];
-
-/** Offset 0x0343 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[24];
-
-/** Offset 0x035B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen1DownscaleAmp[24];
-
-/** Offset 0x0373 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[24];
-
-/** Offset 0x038B - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen2DownscaleAmp[24];
-
-/** Offset 0x03A3 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[24];
-
-/** Offset 0x03BB - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
- PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchPcieHsioTxGen3DownscaleAmp[24];
-
-/** Offset 0x03D3 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen1DeEmphEnable[24];
-
-/** Offset 0x03EB - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
- PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen1DeEmph[24];
-
-/** Offset 0x0403 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[24];
-
-/** Offset 0x041B - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
- PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph3p5[24];
-
-/** Offset 0x0433 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[24];
-
-/** Offset 0x044B - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
- PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
-**/
- UINT8 PchPcieHsioTxGen2DeEmph6p0[24];
-
-/** Offset 0x0463 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
-
-/** Offset 0x046B - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen1EqBoostMag[8];
-
-/** Offset 0x0473 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
-
-/** Offset 0x047B - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen2EqBoostMag[8];
-
-/** Offset 0x0483 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
-
-/** Offset 0x048B - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
- PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
-**/
- UINT8 PchSataHsioRxGen3EqBoostMag[8];
-
-/** Offset 0x0493 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
-
-/** Offset 0x049B - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen1DownscaleAmp[8];
-
-/** Offset 0x04A3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
-
-/** Offset 0x04AB - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen2DownscaleAmp[8];
-
-/** Offset 0x04B3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
-
-/** Offset 0x04BB - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
- PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
-**/
- UINT8 PchSataHsioTxGen3DownscaleAmp[8];
-
-/** Offset 0x04C3 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen1DeEmphEnable[8];
-
-/** Offset 0x04CB - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen1DeEmph[8];
-
-/** Offset 0x04D3 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen2DeEmphEnable[8];
-
-/** Offset 0x04DB - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen2DeEmph[8];
-
-/** Offset 0x04E3 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
- 0: Disable; 1: Enable.
-**/
- UINT8 PchSataHsioTxGen3DeEmphEnable[8];
-
-/** Offset 0x04EB - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
- PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
-**/
- UINT8 PchSataHsioTxGen3DeEmph[8];
-
-/** Offset 0x04F3 - PCH LPC Enhance the port 8xh decoding
- Original LPC only decodes one byte of port 80h.
- $EN_DIS
-**/
- UINT8 PchLpcEnhancePort8xhDecoding;
-
-/** Offset 0x04F4 - PCH Acpi Base
- Power management I/O base address. Default is 0x1800.
-**/
- UINT16 PchAcpiBase;
-
-/** Offset 0x04F6 - PCH Port80 Route
- Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
- $EN_DIS
-**/
- UINT8 PchPort80Route;
-
-/** Offset 0x04F7 - Enable SMBus ARP support
- Enable SMBus ARP support.
- $EN_DIS
-**/
- UINT8 SmbusArpEnable;
-
-/** Offset 0x04F8 - SMBUS Base Address
- SMBUS Base Address (IO space).
-**/
- UINT16 PchSmbusIoBase;
-
-/** Offset 0x04FA - Number of RsvdSmbusAddressTable.
- The number of elements in the RsvdSmbusAddressTable.
-**/
- UINT8 PchNumRsvdSmbusAddresses;
-
-/** Offset 0x04FB
-**/
- UINT8 UnusedUpdSpace8;
-
-/** Offset 0x04FC - Point of RsvdSmbusAddressTable
- Array of addresses reserved for non-ARP-capable SMBus devices.
-**/
- UINT32 RsvdSmbusAddressTablePtr;
-
-/** Offset 0x0500 - Trace Hub Memory Region 0
- Trace Hub Memory Region 0.
-**/
- UINT32 TraceHubMemReg0Size;
-
-/** Offset 0x0504 - Trace Hub Memory Region 1
- Trace Hub Memory Region 1.
-**/
- UINT32 TraceHubMemReg1Size;
-
-/** Offset 0x0508 - Enable PCIE RP Mask
- Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
- for port1, bit1 for port2, and so on.
-**/
- UINT32 PcieRpEnableMask;
-
-/** Offset 0x050C - Debug Interfaces
- Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
- BIT2 - Not used.
-**/
- UINT8 PcdDebugInterfaceFlags;
-
-/** Offset 0x050D - SerialIo Uart Number Selection
- Select SerialIo Uart Controller for debug.
- 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
-**/
- UINT8 PcdSerialIoUartNumber;
-
-/** Offset 0x050E - ISA Serial Base selection
- Select ISA Serial Base address. Default is 0x3F8.
- 0:0x3F8, 1:0x2F8
-**/
- UINT8 PcdIsaSerialUartBase;
-
-/** Offset 0x050F - PCH Pm Pcie Pll Ssc
- Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
- BIOS override.
-**/
- UINT8 PchPmPciePllSsc;
-
-/** Offset 0x0510 - Enable or Disable Peci C10 Reset command
- Enable or Disable Peci C10 Reset command; <b>0: Disable;</b> 1: Enable.
- $EN_DIS
-**/
- UINT8 PeciC10Reset;
-
-/** Offset 0x0511 - Enable or Disable Peci Sx Reset command
- Enable or Disable Peci Sx Reset command; <b>0: Disable;</b> 1: Enable.
- $EN_DIS
-**/
- UINT8 PeciSxReset;
-
-/** Offset 0x0512 - PcdSerialDebugBaudRate
- Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
- 3:9600, 4:19200, 6:56700, 7:115200
-**/
- UINT8 PcdSerialDebugBaudRate;
-
-/** Offset 0x0513 - PcdSerialDebugLevel
- Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
- Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
- Info & Verbose
- 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
- Error Warnings and Info, 5:Load Error Warnings Info and Verbose
-**/
- UINT8 PcdSerialDebugLevel;
-
-/** Offset 0x0514 - Enable or Disable EV Loader
- Enable or Disable EV Loader; <b>0: Disable;</b> 1: Enable.
- $EN_DIS
-**/
- UINT8 EvLoader;
-
-/** Offset 0x0515 - GT PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
- 0x0:0xFF
-**/
- UINT8 GtPllVoltageOffset;
-
-/** Offset 0x0516 - Ring PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
- 0x0:0xFF
-**/
- UINT8 RingPllVoltageOffset;
-
-/** Offset 0x0517 - System Agent PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
- 0x0:0xFF
-**/
- UINT8 SaPllVoltageOffset;
-
-/** Offset 0x0518 - Memory Controller PLL voltage offset
- Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
- 0x0:0xFF
-**/
- UINT8 McPllVoltageOffset;
-
-/** Offset 0x0519 - Realtime Memory Timing
- 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
- realtime memory timing changes after MRC_DONE.
- 0: Disabled, 1: Enabled
-**/
- UINT8 RealtimeMemoryTiming;
-
-/** Offset 0x051A - AVX3 Ratio Offset
- 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
- vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
-**/
- UINT8 Avx3RatioOffset;
-
-/** Offset 0x051B - Ask MRC to clear memory content
- Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
- $EN_DIS
-**/
- UINT8 CleanMemory;
-
-/** Offset 0x051C
-**/
- UINT8 ReservedFspmUpd[4];
-} FSP_M_CONFIG;
-
-/** Fsp M Test Configuration
-**/
-typedef struct {
-
-/** Offset 0x0520
-**/
- UINT32 Signature;
-
-/** Offset 0x0524 - Skip external display device scanning
- Enable: Do not scan for external display device, Disable (Default): Scan external
- display devices
- $EN_DIS
-**/
- UINT8 SkipExtGfxScan;
-
-/** Offset 0x0525 - Generate BIOS Data ACPI Table
- Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
- $EN_DIS
-**/
- UINT8 BdatEnable;
-
-/** Offset 0x0526 - Detect External Graphics device for LegacyOpROM
- Detect and report if external graphics device only support LegacyOpROM or not (to
- support CSM auto-enable). Enable(Default)=1, Disable=0
- $EN_DIS
-**/
- UINT8 ScanExtGfxForLegacyOpRom;
-
-/** Offset 0x0527 - Lock PCU Thermal Management registers
- Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
- $EN_DIS
-**/
- UINT8 LockPTMregs;
-
-/** Offset 0x0528 - Enable/Disable DmiVc1
- Enable/Disable DmiVc1. Enable = 1, Disable (Default) = 0
- $EN_DIS
-**/
- UINT8 DmiVc1;
-
-/** Offset 0x0529 - Enable/Disable DmiVcm
- Enable/Disable DmiVcm. Enable (Default) = 1, Disable = 0
- $EN_DIS
-**/
- UINT8 DmiVcm;
-
-/** Offset 0x052A - DMI Max Link Speed
- Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
- Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
- 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
-**/
- UINT8 DmiMaxLinkSpeed;
-
-/** Offset 0x052B - DMI Equalization Phase 2
- DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
- AUTO - Use the current default method
- 0:Disable phase2, 1:Enable phase2, 2:Auto
-**/
- UINT8 DmiGen3EqPh2Enable;
-
-/** Offset 0x052C - DMI Gen3 Equalization Phase3
- DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 DmiGen3EqPh3Method;
-
-/** Offset 0x052D - Phase2 EQ enable on the PEG 0:1:0.
- Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
- Enable phase 2, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Peg0Gen3EqPh2Enable;
-
-/** Offset 0x052E - Phase2 EQ enable on the PEG 0:1:1.
- Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
- Enable phase 2, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Peg1Gen3EqPh2Enable;
-
-/** Offset 0x052F - Phase2 EQ enable on the PEG 0:1:2.
- Phase2 EQ enable on the PEG 0:1:0. Disabled(0x0): Disable phase 2, Enabled(0x1):
- Enable phase 2, Auto(0x2)(Default): Use the current default method
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Peg2Gen3EqPh2Enable;
-
-/** Offset 0x0530 - Phase3 EQ method on the PEG 0:1:0.
- PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 Peg0Gen3EqPh3Method;
-
-/** Offset 0x0531 - Phase3 EQ method on the PEG 0:1:1.
- PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 Peg1Gen3EqPh3Method;
-
-/** Offset 0x0532 - Phase3 EQ method on the PEG 0:1:2.
- PEG Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
- HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
- Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
- EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
- Phase1), Disabled(0x4): Bypass Equalization Phase 3
- 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
-**/
- UINT8 Peg2Gen3EqPh3Method;
-
-/** Offset 0x0533 - Enable/Disable PEG GEN3 Static EQ Phase1 programming
- Program PEG Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
- Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
- $EN_DIS
-**/
- UINT8 PegGen3ProgramStaticEq;
-
-/** Offset 0x0534 - PEG Gen3 SwEq Always Attempt
- Gen3 Software Equalization will be executed every boot. Disabled(0x0)(Default):
- Reuse EQ settings saved/restored from NVRAM whenever possible, Enabled(0x1): Re-test
- and generate new EQ values every boot, not recommended
- 0:Disable, 1:Enable
-**/
- UINT8 Gen3SwEqAlwaysAttempt;
-
-/** Offset 0x0535 - Select number of TxEq presets to test in the PCIe/DMI SwEq
- Select number of TxEq presets to test in the PCIe/DMI SwEq. P7,P3,P5(0x0): Test
- Presets 7, 3, and 5, P0-P9(0x1): Test Presets 0-9, Auto(0x2)(Default): Use the
- current default method (Default)Auto will test Presets 7, 3, and 5. It is possible
- for this default to change over time;using Auto will ensure Reference Code always
- uses the latest default settings
- 0:P7 P3 P5, 1:P0 to P9, 2:Auto
-**/
- UINT8 Gen3SwEqNumberOfPresets;
-
-/** Offset 0x0536 - Enable use of the Voltage Offset and Centering Test in the PCIe SwEq
- Enable use of the Voltage Offset and Centering Test in the PCIe Software Equalization
- Algorithm. Disabled(0x0): Disable VOC Test, Enabled(0x1): Enable VOC Test, Auto(0x2)(Default):
- Use the current default
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 Gen3SwEqEnableVocTest;
-
-/** Offset 0x0537 - PPCIe Rx Compliance Testing Mode
- Disabled(0x0)(Default): Normal Operation - Disable PCIe Rx Compliance testing, Enabled(0x1):
- PCIe Rx Compliance Test Mode - PEG controller is in Rx Compliance Testing Mode;
- it should only be set when doing PCIe compliance testing
- $EN_DIS
-**/
- UINT8 PegRxCemTestingMode;
-
-/** Offset 0x0538 - PCIe Rx Compliance Loopback Lane When PegRxCemTestingMode is Enabled
- the specificied Lane (0 - 15) will be used for RxCEMLoopback. Default is Lane 0
-**/
- UINT8 PegRxCemLoopbackLane;
-
-/** Offset 0x0539 - Generate PCIe BDAT Margin Table
- Set this policy to enable the generation and addition of PCIe margin data to the
- BDAT table. Disabled(0x0)(Default): Normal Operation - Disable PCIe BDAT margin
- data generation, Enable(0x1): Generate PCIe BDAT margin data
- $EN_DIS
-**/
- UINT8 PegGenerateBdatMarginTable;
-
-/** Offset 0x053A
-**/
- UINT8 UnusedUpdSpace9[6];
-
-/** Offset 0x0540 - PCIe Non-Protocol Awareness for Rx Compliance Testing
- Set this policy to enable the generation and addition of PCIe margin data to the
- BDAT table. Disabled(0x0)(Default): Normal Operation - Disable non-protocol awareness,
- Enable(0x1): Non-Protocol Awareness Enabled - Enable non-protocol awareness for
- compliance testing
- $EN_DIS
-**/
- UINT8 PegRxCemNonProtocolAwareness;
-
-/** Offset 0x0541 - PCIe Override RxCTLE
- Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
- Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
- peak values unmodified
- $EN_DIS
-**/
- UINT8 PegGen3RxCtleOverride;
-
-/** Offset 0x0542 - Rsvd
- Disable(0x0)(Default): Normal Operation - RxCTLE adaptive behavior enabled, Enable(0x1):
- Override RxCTLE - Disable RxCTLE adaptive behavior to keep the configured RxCTLE
- peak values unmodified
- $EN_DIS
-**/
- UINT8 PegGen3Rsvd;
-
-/** Offset 0x0543 - Panel Power Enable
- Control for enabling/disabling VDD force bit (Required only for early enabling of
- eDP panel). 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 PanelPowerEnable;
-
-/** Offset 0x0544 - PEG Gen3 Root port preset values per lane
- Used for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
-**/
- UINT8 PegGen3RootPortPreset[16];
-
-/** Offset 0x0554 - PEG Gen3 End port preset values per lane
- Used for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
-**/
- UINT8 PegGen3EndPointPreset[16];
-
-/** Offset 0x0564 - PEG Gen3 End port Hint values per lane
- Used for programming PEG Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
-**/
- UINT8 PegGen3EndPointHint[16];
-
-/** Offset 0x0574 - Jitter Dwell Time for PCIe Gen3 Software Equalization
- Range: 0-65535, default is 1000. @warning Do not change from the default
-**/
- UINT16 Gen3SwEqJitterDwellTime;
-
-/** Offset 0x0576 - Jitter Error Target for PCIe Gen3 Software Equalization
- Range: 0-65535, default is 1. @warning Do not change from the default
-**/
- UINT16 Gen3SwEqJitterErrorTarget;
-
-/** Offset 0x0578 - VOC Dwell Time for PCIe Gen3 Software Equalization
- Range: 0-65535, default is 10000. @warning Do not change from the default
-**/
- UINT16 Gen3SwEqVocDwellTime;
-
-/** Offset 0x057A - VOC Error Target for PCIe Gen3 Software Equalization
- Range: 0-65535, default is 2. @warning Do not change from the default
-**/
- UINT16 Gen3SwEqVocErrorTarget;
-
-/** Offset 0x057C - SaPreMemTestRsvd
- Reserved for SA Pre-Mem Test
- $EN_DIS
-**/
- UINT8 SaPreMemTestRsvd[4];
-
-/** Offset 0x0580 - BiosAcmBase
- Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
-**/
- UINT64 BiosAcmBase;
-
-/** Offset 0x0588 - BiosAcmSize
- Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
-**/
- UINT32 BiosAcmSize;
-
-/** Offset 0x058C - TgaSize
- Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
-**/
- UINT32 TgaSize;
-
-/** Offset 0x0590 - TxtLcpPdBase
- Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
-**/
- UINT64 TxtLcpPdBase;
-
-/** Offset 0x0598 - TxtLcpPdSize
- Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
-**/
- UINT64 TxtLcpPdSize;
-
-/** Offset 0x05A0 - TotalFlashSize
- Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
-**/
- UINT16 TotalFlashSize;
-
-/** Offset 0x05A2 - BiosSize
- Enable/Disable. 0: Disable, define default value of BiosSize , 1: enable
-**/
- UINT16 BiosSize;
-
-/** Offset 0x05A4 - PCH Dci Enable
- Enable/disable PCH Dci.
- $EN_DIS
-**/
- UINT8 PchDciEn;
-
-/** Offset 0x05A5 - PCH Dci Auto Detect
- Deprecated
- $EN_DIS
-**/
- UINT8 PchDciAutoDetect;
-
-/** Offset 0x05A6 - Smbus dynamic power gating
- Disable or Enable Smbus dynamic power gating.
- $EN_DIS
-**/
- UINT8 SmbusDynamicPowerGating;
-
-/** Offset 0x05A7 - Disable and Lock Watch Dog Register
- Set 1 to clear WDT status, then disable and lock WDT registers.
- $EN_DIS
-**/
- UINT8 WdtDisableAndLock;
-
-/** Offset 0x05A8 - SMBUS SPD Write Disable
- Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
- Disable bit. For security recommendations, SPD write disable bit must be set.
- $EN_DIS
-**/
- UINT8 SmbusSpdWriteDisable;
-
-/** Offset 0x05A9 - ChipsetInit HECI message
- Enable/Disable. 0: Disable, 1: enable, Enable or disable ChipsetInit HECI message.
- If disabled, it prevents from sending ChipsetInit HECI message.
- $EN_DIS
-**/
- UINT8 ChipsetInitMessage;
-
-/** Offset 0x05AA - Bypass ChipsetInit sync reset.
- 0: disable, 1: enable, Set Enable to bypass the reset after ChipsetInit HECI message.
- $EN_DIS
-**/
- UINT8 BypassPhySyncReset;
-
-/** Offset 0x05AB - Force ME DID Init Status
- Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, 4:
- Memory not preserved across reset, Set ME DID init stat value
- $EN_DIS
-**/
- UINT8 DidInitStat;
-
-/** Offset 0x05AC - CPU Replaced Polling Disable
- Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
- $EN_DIS
-**/
- UINT8 DisableCpuReplacedPolling;
-
-/** Offset 0x05AD - ME DID Message
- Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable will prevent
- the DID message from being sent)
- $EN_DIS
-**/
- UINT8 SendDidMsg;
-
-/** Offset 0x05AE - Retry mechanism for HECI APIs
- Test, 0: disable, 1: enable, Enable/Disable HECI retry.
- $EN_DIS
-**/
- UINT8 DisableHeciRetry;
-
-/** Offset 0x05AF - Check HECI message before send
- Test, 0: disable, 1: enable, Enable/Disable message check.
- $EN_DIS
-**/
- UINT8 DisableMessageCheck;
-
-/** Offset 0x05B0 - Skip MBP HOB
- Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
- $EN_DIS
-**/
- UINT8 SkipMbpHob;
-
-/** Offset 0x05B1 - HECI2 Interface Communication
- Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
- $EN_DIS
-**/
- UINT8 HeciCommunication2;
-
-/** Offset 0x05B2 - Enable KT device
- Test, 0: disable, 1: enable, Enable or Disable KT device.
- $EN_DIS
-**/
- UINT8 KtDeviceEnable;
-
-/** Offset 0x05B3 - Enable IDEr
- Test, 0: disable, 1: enable, Enable or Disable IDEr.
- $EN_DIS
-**/
- UINT8 IderDeviceEnable;
-
-/** Offset 0x05B4
-**/
- UINT8 ReservedFspmTestUpd[12];
-} FSP_M_TEST_CONFIG;
-
-/** Fsp M UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSPM_ARCH_UPD FspmArchUpd;
-
-/** Offset 0x0040
-**/
- FSP_M_CONFIG FspmConfig;
-
-/** Offset 0x0520
-**/
- FSP_M_TEST_CONFIG FspmTestConfig;
-
-/** Offset 0x05C0
-**/
- UINT8 UnusedUpdSpace10[134];
-
-/** Offset 0x0646
-**/
- UINT16 UpdTerminator;
-} FSPM_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
deleted file mode 100644
index 0209245151..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ /dev/null
@@ -1,2991 +0,0 @@
-/** @file
-
-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-
-#ifndef __FSPSUPD_H__
-#define __FSPSUPD_H__
-
-#include <FspUpd.h>
-
-#pragma pack(1)
-
-
-#include <ConfigBlock/CpuConfigFspData.h>
-///
-/// Azalia Header structure
-///
-typedef struct {
- UINT16 VendorId; ///< Codec Vendor ID
- UINT16 DeviceId; ///< Codec Device ID
- UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
- UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
- UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
- UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
-} AZALIA_HEADER;
-
-///
-/// Audio Azalia Verb Table structure
-///
-typedef struct {
- AZALIA_HEADER Header; ///< AZALIA PCH header
- UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
-} AUDIO_AZALIA_VERB_TABLE;
-
-///
-/// Refer to the definition of PCH_INT_PIN
-///
-typedef enum {
- SiPchNoInt, ///< No Interrupt Pin
- SiPchIntA,
- SiPchIntB,
- SiPchIntC,
- SiPchIntD
-} SI_PCH_INT_PIN;
-///
-/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
-///
-typedef struct {
- UINT8 Device; ///< Device number
- UINT8 Function; ///< Device function
- UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
- UINT8 Irq; ///< IRQ to be set for device.
-} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-
-#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
-
-
-/** Fsp S Configuration
-**/
-typedef struct {
-
-/** Offset 0x0020 - Logo Pointer
- Points to PEI Display Logo Image
-**/
- UINT32 LogoPtr;
-
-/** Offset 0x0024 - Logo Size
- Size of PEI Display Logo Image
-**/
- UINT32 LogoSize;
-
-/** Offset 0x0028 - Graphics Configuration Ptr
- Points to VBT
-**/
- UINT32 GraphicsConfigPtr;
-
-/** Offset 0x002C - Enable Device 4
- Enable/disable Device 4
- $EN_DIS
-**/
- UINT8 Device4Enable;
-
-/** Offset 0x002D - Enable Intel HD Audio (Azalia)
- Enable/disable Azalia controller.
- $EN_DIS
-**/
- UINT8 PchHdaEnable;
-
-/** Offset 0x002E - Enable HD Audio DSP
- Enable/disable HD Audio DSP feature.
- $EN_DIS
-**/
- UINT8 PchHdaDspEnable;
-
-/** Offset 0x002F - Select HDAudio IoBuffer Ownership
- Indicates the ownership of the I/O buffer between Intel HD Audio link vs I2S0 /
- I2S port. 0: Intel HD-Audio link owns all the I/O buffers. 1: Intel HD-Audio link
- owns 4 of the I/O buffers for 1 HD-Audio codec connection, and I2S1 port owns 4
- of the I/O buffers for 1 I2S codec connection. 2: Reserved. 3: I2S0 and I2S1 ports
- own all the I/O buffers.
- 0:HD-A Link, 1:Shared HD-A Link and I2S Port, 3:I2S Ports
-**/
- UINT8 PchHdaIoBufferOwnership;
-
-/** Offset 0x0030 - Enable CIO2 Controller
- Enable/disable SKYCAM CIO2 Controller.
- $EN_DIS
-**/
- UINT8 PchCio2Enable;
-
-/** Offset 0x0031 - Enable eMMC Controller
- Enable/disable eMMC Controller.
- $EN_DIS
-**/
- UINT8 ScsEmmcEnabled;
-
-/** Offset 0x0032 - Enable eMMC HS400 Mode
- Enable eMMC HS400 Mode.
- $EN_DIS
-**/
- UINT8 ScsEmmcHs400Enabled;
-
-/** Offset 0x0033 - Enable SdCard Controller
- Enable/disable SD Card Controller.
- $EN_DIS
-**/
- UINT8 ScsSdCardEnabled;
-
-/** Offset 0x0034 - Enable PCH ISH Controller
- Enable/disable ISH Controller.
- $EN_DIS
-**/
- UINT8 PchIshEnable;
-
-/** Offset 0x0035 - Show SPI controller
- Enable/disable to show SPI controller.
- $EN_DIS
-**/
- UINT8 ShowSpiController;
-
-/** Offset 0x0036 - Flash Configuration Lock Down
- Enable/disable flash lock down. If platform decides to skip this programming, it
- must lock SPI flash register DLOCK, FLOCKDN, and WRSDIS before end of post.
- $EN_DIS
-**/
- UINT8 SpiFlashCfgLockDown;
-
-/** Offset 0x0037
-**/
- UINT8 UnusedUpdSpace0;
-
-/** Offset 0x0038 - MicrocodeRegionBase
- Memory Base of Microcode Updates
-**/
- UINT32 MicrocodeRegionBase;
-
-/** Offset 0x003C - MicrocodeRegionSize
- Size of Microcode Updates
-**/
- UINT32 MicrocodeRegionSize;
-
-/** Offset 0x0040 - Turbo Mode
- Enable/Disable Turbo mode. 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 TurboMode;
-
-/** Offset 0x0041 - Enable SATA SALP Support
- Enable/disable SATA Aggressive Link Power Management.
- $EN_DIS
-**/
- UINT8 SataSalpSupport;
-
-/** Offset 0x0042 - Enable SATA ports
- Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
- and so on.
-**/
- UINT8 SataPortsEnable[8];
-
-/** Offset 0x004A - Enable SATA DEVSLP Feature
- Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
- port, byte0 for port0, byte1 for port1, and so on.
-**/
- UINT8 SataPortsDevSlp[8];
-
-/** Offset 0x0052 - Enable USB2 ports
- Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb20Enable[16];
-
-/** Offset 0x0062 - Enable USB3 ports
- Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
- port1, and so on.
-**/
- UINT8 PortUsb30Enable[10];
-
-/** Offset 0x006C - Enable xDCI controller
- Enable/disable to xDCI controller.
- $EN_DIS
-**/
- UINT8 XdciEnable;
-
-/** Offset 0x006D - Enable XHCI SSIC Enable
- Enable/disable XHCI SSIC port.
- $EN_DIS
-**/
- UINT8 SsicPortEnable;
-
-/** Offset 0x006E
-**/
- UINT8 UnusedUpdSpace1;
-
-/** Offset 0x006F - Number of DevIntConfig Entry
- Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
- must not be NULL.
-**/
- UINT8 NumOfDevIntConfig;
-
-/** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
- The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
-**/
- UINT32 DevIntConfigPtr;
-
-/** Offset 0x0074 - Enable SerialIo Device Mode
- 0:Disabled, 1:ACPI Mode, 2:PCI Mode, 3:Hidden mode, 4:Legacy UART mode - Enable/disable
- SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5,SPI0,SPI1,UART0,UART1,UART2 device mode
- respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
-**/
- UINT8 SerialIoDevMode[11];
-
-/** Offset 0x007F - PIRQx to IRQx Map Config
- PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
- PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
- 8259 PCI mode.
-**/
- UINT8 PxRcConfig[8];
-
-/** Offset 0x0087 - Select GPIO IRQ Route
- GPIO IRQ Select. The valid value is 14 or 15.
-**/
- UINT8 GpioIrqRoute;
-
-/** Offset 0x0088 - Select SciIrqSelect
- SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
-**/
- UINT8 SciIrqSelect;
-
-/** Offset 0x0089 - Select TcoIrqSelect
- TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
-**/
- UINT8 TcoIrqSelect;
-
-/** Offset 0x008A - Enable/Disable Tco IRQ
- Enable/disable TCO IRQ
- $EN_DIS
-**/
- UINT8 TcoIrqEnable;
-
-/** Offset 0x008B - PCH HDA Verb Table Entry Number
- Number of Entries in Verb Table.
-**/
- UINT8 PchHdaVerbTableEntryNum;
-
-/** Offset 0x008C - PCH HDA Verb Table Pointer
- Pointer to Array of pointers to Verb Table.
-**/
- UINT32 PchHdaVerbTablePtr;
-
-/** Offset 0x0090
-**/
- UINT8 UnusedUpdSpace2;
-
-/** Offset 0x0091 - Enable SATA
- Enable/disable SATA controller.
- $EN_DIS
-**/
- UINT8 SataEnable;
-
-/** Offset 0x0092 - SATA Mode
- Select SATA controller working mode.
- 0:AHCI, 1:RAID
-**/
- UINT8 SataMode;
-
-/** Offset 0x0093 - USB Per Port HS Preemphasis Bias
- USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
-**/
- UINT8 Usb2AfePetxiset[16];
-
-/** Offset 0x00A3 - USB Per Port HS Transmitter Bias
- USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
- 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
-**/
- UINT8 Usb2AfeTxiset[16];
-
-/** Offset 0x00B3 - USB Per Port HS Transmitter Emphasis
- USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
- 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
-**/
- UINT8 Usb2AfePredeemp[16];
-
-/** Offset 0x00C3 - USB Per Port Half Bit Pre-emphasis
- USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
- One byte for each port.
-**/
- UINT8 Usb2AfePehalfbit[16];
-
-/** Offset 0x00D3 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
- Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmphEnable[10];
-
-/** Offset 0x00DD - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
- USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
- <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
-**/
- UINT8 Usb3HsioTxDeEmph[10];
-
-/** Offset 0x00E7 - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
- Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
- in arrary can be between 0-1. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmpEnable[10];
-
-/** Offset 0x00F1 - USB 3.0 TX Output Downscale Amplitude Adjustment
- USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
- = 00h</b>. One byte for each port.
-**/
- UINT8 Usb3HsioTxDownscaleAmp[10];
-
-/** Offset 0x00FB - Enable LAN
- Enable/disable LAN controller.
- $EN_DIS
-**/
- UINT8 PchLanEnable;
-
-/** Offset 0x00FC - Delay USB PDO Programming
- Enable/disable delay of PDO programming for USB from PEI phase to DXE phase. 0:
- disable, 1: enable
- $EN_DIS
-**/
- UINT8 DelayUsbPdoProgramming;
-
-/** Offset 0x00FD
-**/
- UINT8 UnusedUpdSpace3[23];
-
-/** Offset 0x0114 - Enable PCIE RP CLKREQ Support
- Enable/disable PCIE Root Port CLKREQ support. 0: disable, 1: enable. One byte for
- each port, byte0 for port1, byte1 for port2, and so on.
-**/
- UINT8 PcieRpClkReqSupport[24];
-
-/** Offset 0x012C - Configure CLKREQ Number
- Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can
- be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on.
-**/
- UINT8 PcieRpClkReqNumber[24];
-
-/** Offset 0x0144
-**/
- UINT8 UnusedUpdSpace4[5];
-
-/** Offset 0x0149 - HECI3 state
- The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
- 0: disable, 1: enable
- $EN_DIS
-**/
- UINT8 Heci3Enabled;
-
-/** Offset 0x014A
-**/
- UINT8 UnusedUpdSpace5[9];
-
-/** Offset 0x0153 - AMT Switch
- Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
- $EN_DIS
-**/
- UINT8 AmtEnabled;
-
-/** Offset 0x0154 - WatchDog Timer Switch
- Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer.
- $EN_DIS
-**/
- UINT8 WatchDog;
-
-/** Offset 0x0155 - ASF Switch
- Enable/Disable. 0: Disable, 1: enable, Enable or disable ASF functionality.
- $EN_DIS
-**/
- UINT8 AsfEnabled;
-
-/** Offset 0x0156 - Manageability Mode set by Mebx
- Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
- $EN_DIS
-**/
- UINT8 ManageabilityMode;
-
-/** Offset 0x0157 - PET Progress
- Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
- PET Events.
- $EN_DIS
-**/
- UINT8 FwProgress;
-
-/** Offset 0x0158 - OS Timer
- 16 bits Value, Set OS watchdog timer.
- $EN_DIS
-**/
- UINT16 WatchDogTimerOs;
-
-/** Offset 0x015A - BIOS Timer
- 16 bits Value, Set BIOS watchdog timer.
- $EN_DIS
-**/
- UINT16 WatchDogTimerBios;
-
-/** Offset 0x015C - SOL Switch
- Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx
- $EN_DIS
-**/
- UINT8 AmtSolEnabled;
-
-/** Offset 0x015D - Configure CLKSRC Number
- Configure Root Port CLKSRC Number. Each value in arrary can be between 0-6 for valid
- clock numbers or 0x1F for an invalid number. One byte for each port, byte0 for
- port1, byte1 for port2, and so on.
-**/
- UINT8 PcieRpClkSrcNumber[24];
-
-/** Offset 0x0175
-**/
- UINT8 UnusedUpdSpace6[139];
-
-/** Offset 0x0200 - Subsystem Vendor ID for SA devices
- Subsystem ID that will be programmed to SA devices: Default SubSystemVendorId=0x8086
-**/
- UINT16 DefaultSvid;
-
-/** Offset 0x0202 - Subsystem Device ID for SA devices
- Subsystem ID that will be programmed to SA devices: Default SubSystemId=0x2015
-**/
- UINT16 DefaultSid;
-
-/** Offset 0x0204 - Enable/Disable SA CRID
- Enable: SA CRID, Disable (Default): SA CRID
- $EN_DIS
-**/
- UINT8 CridEnable;
-
-/** Offset 0x0205 - DMI ASPM
- 0=Disable, 2(Default)=L1
- 0:Disable, 2:L1
-**/
- UINT8 DmiAspm;
-
-/** Offset 0x0206 - PCIe Physical Slot Number per root port
- Physical Slot Number per root port
-**/
- UINT16 PegPhysicalSlotNumber[3];
-
-/** Offset 0x020C - PCIe DeEmphasis control per root port
- 0: -6dB, 1(Default): -3.5dB
- 0:-6dB, 1:-3.5dB
-**/
- UINT8 PegDeEmphasis[3];
-
-/** Offset 0x020F - PCIe Slot Power Limit value per root port
- Slot power limit value per root port
-**/
- UINT8 PegSlotPowerLimitValue[3];
-
-/** Offset 0x0212 - PCIe Slot Power Limit scale per root port
- Slot power limit scale per root port
- 0:1.0x, 1:0.1x, 2:0.01x, 3:0x001x
-**/
- UINT8 PegSlotPowerLimitScale[3];
-
-/** Offset 0x0215 - Enable/Disable PavpEnable
- Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
- $EN_DIS
-**/
- UINT8 PavpEnable;
-
-/** Offset 0x0216 - CdClock Frequency selection
- 0=308.57 Mhz, 1=337.5 Mhz, 2=432 Mhz, 3=450 Mhz, 4=540 Mhz, 5=617.14 Mhz, 6(Default)= 675 Mhz
- 0: 308.57 Mhz, 1: 337.5 Mhz, 2: 432 Mhz, 3: 450 Mhz, 4: 540 Mhz, 5: 617.14 Mhz,
- 6: 675 Mhz
-**/
- UINT8 CdClock;
-
-/** Offset 0x0217 - Enable/Disable PeiGraphicsPeimInit
- Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
- $EN_DIS
-**/
- UINT8 PeiGraphicsPeimInit;
-
-/** Offset 0x0218 - Enable/Disable SA IMGU(SKYCAM)
- Enable(Default): Enable SA IMGU(SKYCAM), Disable: Disable SA IMGU(SKYCAM)
- $EN_DIS
-**/
- UINT8 SaImguEnable;
-
-/** Offset 0x0219 - Enable or disable GMM device
- 0=Disable, 1(Default)=Enable
- $EN_DIS
-**/
- UINT8 GmmEnable;
-
-/** Offset 0x021A - State of X2APIC_OPT_OUT bit in the DMAR table
- 0=Disable/Clear, 1(Default)=Enable/Set
- $EN_DIS
-**/
- UINT8 X2ApicOptOut;
-
-/** Offset 0x021B
-**/
- UINT8 UnusedUpdSpace7[1];
-
-/** Offset 0x021C - Base addresses for VT-d function MMIO access
- Base addresses for VT-d MMIO access per VT-d engine
-**/
- UINT32 VtdBaseAddress[2];
-
-/** Offset 0x0224
-**/
- UINT8 UnusedUpdSpace8[19];
-
-/** Offset 0x0237 - SaPostMemProductionRsvd
- Reserved for SA Post-Mem Production
- $EN_DIS
-**/
- UINT8 SaPostMemProductionRsvd[16];
-
-/** Offset 0x0247
-**/
- UINT8 UnusedUpdSpace9[7];
-
-/** Offset 0x024E - Power State 3 enable/disable
- PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
- For all VR Indexes
-**/
- UINT8 Psi3Enable[5];
-
-/** Offset 0x0253 - Power State 4 enable/disable
- PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
- all VR Indexes
-**/
- UINT8 Psi4Enable[5];
-
-/** Offset 0x0258 - Imon slope correction
- PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
- Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
-**/
- UINT8 ImonSlope[5];
-
-/** Offset 0x025D - Imon offset correction
- PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
- Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
-**/
- UINT8 ImonOffset[5];
-
-/** Offset 0x0262 - Enable/Disable BIOS configuration of VR
- Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
-**/
- UINT8 VrConfigEnable[5];
-
-/** Offset 0x0267 - Thermal Design Current enable/disable
- PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
- Enable.For all VR Indexes
-**/
- UINT8 TdcEnable[5];
-
-/** Offset 0x026C - HECI3 state
- PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
- Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 - 6ms , 7 - 7ms
- , 8 - 8ms , 10 - 10ms.For all VR Indexe
-**/
- UINT8 TdcTimeWindow[5];
-
-/** Offset 0x0271 - Thermal Design Current Lock
- PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
- all VR Indexes
-**/
- UINT8 TdcLock[5];
-
-/** Offset 0x0276 - Platform Psys slope correction
- PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
- 1/100 increment values. Range is 0-200. 125 = 1.25
-**/
- UINT8 PsysSlope;
-
-/** Offset 0x0277 - Platform Psys offset correction
- PCODE MMIO Mailbox: Platform Psys offset correction. <b>0 - Auto</b> Units 1/4,
- Range 0-255. Value of 100 = 100/4 = 25 offset
-**/
- UINT8 PsysOffset;
-
-/** Offset 0x0278 - Acoustic Noise Mitigation feature
- Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
- $EN_DIS
-**/
- UINT8 AcousticNoiseMitigation;
-
-/** Offset 0x0279 - Disable Fast Slew Rate for Deep Package C States for VR IA domain
- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
- feature enabled. <b>0: False</b>; 1: True
- $EN_DIS
-**/
- UINT8 FastPkgCRampDisableIa;
-
-/** Offset 0x027A - Slew Rate configuration for Deep Package C States for VR IA domain
- Slew Rate configuration for Deep Package C States for VR IA domain based on Acoustic
- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
-**/
- UINT8 SlowSlewRateForIa;
-
-/** Offset 0x027B - Slew Rate configuration for Deep Package C States for VR GT domain
- Slew Rate configuration for Deep Package C States for VR GT domain based on Acoustic
- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
-**/
- UINT8 SlowSlewRateForGt;
-
-/** Offset 0x027C - Slew Rate configuration for Deep Package C States for VR SA domain
- Slew Rate configuration for Deep Package C States for VR SA domain based on Acoustic
- Noise Mitigation feature enabled. <b>0: Fast/2</b>; 1: Fast/4; 2: Fast/8; 3: Fast/16
- 0: Fast/2, 1: Fast/4, 2: Fast/8, 3: Fast/16
-**/
- UINT8 SlowSlewRateForSa;
-
-/** Offset 0x027D
-**/
- UINT8 UnusedUpdSpace10[9];
-
-/** Offset 0x0286 - Thermal Design Current current limit
- PCODE MMIO Mailbox: Thermal Design Current current limit. Specified in 1/8A units.
- Range is 0-4095. 1000 = 125A. <b>0: Auto</b>. For all VR Indexes
-**/
- UINT16 TdcPowerLimit[5];
-
-/** Offset 0x0290
-**/
- UINT8 UnusedUpdSpace11[8];
-
-/** Offset 0x0298 - AcLoadline
- PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
- 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
-**/
- UINT16 AcLoadline[5];
-
-/** Offset 0x02A2 - DcLoadline
- PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
- 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
-**/
- UINT16 DcLoadline[5];
-
-/** Offset 0x02AC - Power State 1 Threshold current
- PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is
- 0-128A. Default Value = 20A.
-**/
- UINT16 Psi1Threshold[5];
-
-/** Offset 0x02B6 - Power State 2 Threshold current
- PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is
- 0-128A. Default Value = 5A.
-**/
- UINT16 Psi2Threshold[5];
-
-/** Offset 0x02C0 - Power State 3 Threshold current
- PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is
- 0-128A. Default Value = 1A.
-**/
- UINT16 Psi3Threshold[5];
-
-/** Offset 0x02CA - Icc Max limit
- PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
-**/
- UINT16 IccMax[5];
-
-/** Offset 0x02D4 - VR Voltage Limit
- PCODE MMIO Mailbox: VR Voltage Limit. Range is 0-7999mV.
-**/
- UINT16 VrVoltageLimit[5];
-
-/** Offset 0x02DE
-**/
- UINT8 UnusedUpdSpace12;
-
-/** Offset 0x02DF - Disable Fast Slew Rate for Deep Package C States for VR GT domain
- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
- feature enabled. <b>0: False</b>; 1: True
- $EN_DIS
-**/
- UINT8 FastPkgCRampDisableGt;
-
-/** Offset 0x02E0 - Disable Fast Slew Rate for Deep Package C States for VR SA domain
- Disable Fast Slew Rate for Deep Package C States based on Acoustic Noise Mitigation
- feature enabled. <b>0: False</b>; 1: True
- $EN_DIS
-**/
- UINT8 FastPkgCRampDisableSa;
-
-/** Offset 0x02E1
-**/
- UINT8 UnusedUpdSpace13;
-
-/** Offset 0x02E2 - Enable VR specific mailbox command
- VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
- VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
- command sent for PS4 exit issue. 11b - Reserved.
- $EN_DIS
-**/
- UINT8 SendVrMbxCmd;
-
-/** Offset 0x02E3 - Select VR specific mailbox command to send
- VR specific mailbox commands. <b>000b - no VR specific command sent.</b> 001b -
- VR mailbox command specifically for the MPS IMPV8 VR will be sent. 010b - VR specific
- command sent for PS4 exit issue. 100b - VR specific command sent for MPS VR decay issue.
-**/
- UINT8 SendVrMbxCmd1;
-
-/** Offset 0x02E4 - CpuS3ResumeMtrrData
- Pointer to CPU S3 Resume MTRR Data
-**/
- UINT32 CpuS3ResumeMtrrData;
-
-/** Offset 0x02E8 - Cpu Configuration
- Cpu Configuration data.
-**/
- CPU_CONFIG_FSP_DATA CpuConfig;
-
-/** Offset 0x02F0 - MicrocodePatchAddress
- Pointer to microcode patch that is suitable for this processor.
- 0:Disable, 1:Enable
-**/
- UINT64 MicrocodePatchAddress;
-
-/** Offset 0x02F8 - CpuS3ResumeMtrrDataSize
- Size of S3 resume MTRR data.
-**/
- UINT16 CpuS3ResumeMtrrDataSize;
-
-/** Offset 0x02FA
-**/
- UINT8 UnusedUpdSpace14;
-
-/** Offset 0x02FB - Enable SkyCam PortA Termination override
- Enable/disable PortA Termination override.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortATermOvrEnable;
-
-/** Offset 0x02FC - Enable SkyCam PortB Termination override
- Enable/disable PortB Termination override.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortBTermOvrEnable;
-
-/** Offset 0x02FD - Enable SkyCam PortC Termination override
- Enable/disable PortC Termination override.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortCTermOvrEnable;
-
-/** Offset 0x02FE - Enable SkyCam PortD Termination override
- Enable/disable PortD Termination override.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortDTermOvrEnable;
-
-/** Offset 0x02FF - Enable SkyCam PortA Clk Trim
- Enable/disable PortA Clk Trim.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortATrimEnable;
-
-/** Offset 0x0300 - Enable SkyCam PortB Clk Trim
- Enable/disable PortB Clk Trim.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortBTrimEnable;
-
-/** Offset 0x0301 - Enable SkyCam PortC Clk Trim
- Enable/disable PortC Clk Trim.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortCTrimEnable;
-
-/** Offset 0x0302 - Enable SkyCam PortD Clk Trim
- Enable/disable PortD Clk Trim.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortDTrimEnable;
-
-/** Offset 0x0303 - Enable SkyCam PortA Ctle
- Enable/disable PortA Ctle.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortACtleEnable;
-
-/** Offset 0x0304 - Enable SkyCam PortB Ctle
- Enable/disable PortB Ctle.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortBCtleEnable;
-
-/** Offset 0x0305 - Enable SkyCam PortCD Ctle
- Enable/disable PortCD Ctle.
- $EN_DIS
-**/
- UINT8 PchSkyCamPortCDCtleEnable;
-
-/** Offset 0x0306 - Enable SkyCam PortA Ctle Cap Value
- Enable/disable PortA Ctle Cap Value.
-**/
- UINT8 PchSkyCamPortACtleCapValue;
-
-/** Offset 0x0307 - Enable SkyCam PortB Ctle Cap Value
- Enable/disable PortB Ctle Cap Value.
-**/
- UINT8 PchSkyCamPortBCtleCapValue;
-
-/** Offset 0x0308 - Enable SkyCam PortCD Ctle Cap Value
- Enable/disable PortCD Ctle Cap Value.
-**/
- UINT8 PchSkyCamPortCDCtleCapValue;
-
-/** Offset 0x0309 - Enable SkyCam PortA Ctle Res Value
- Enable/disable PortA Ctle Res Value.
-**/
- UINT8 PchSkyCamPortACtleResValue;
-
-/** Offset 0x030A - Enable SkyCam PortB Ctle Res Value
- Enable/disable PortB Ctle Res Value.
-**/
- UINT8 PchSkyCamPortBCtleResValue;
-
-/** Offset 0x030B - Enable SkyCam PortCD Ctle Res Value
- Enable/disable PortCD Ctle Res Value.
-**/
- UINT8 PchSkyCamPortCDCtleResValue;
-
-/** Offset 0x030C - Enable SkyCam PortA Clk Trim Value
- Enable/disable PortA Clk Trim Value.
-**/
- UINT8 PchSkyCamPortAClkTrimValue;
-
-/** Offset 0x030D - Enable SkyCam PortB Clk Trim Value
- Enable/disable PortB Clk Trim Value.
-**/
- UINT8 PchSkyCamPortBClkTrimValue;
-
-/** Offset 0x030E - Enable SkyCam PortC Clk Trim Value
- Enable/disable PortC Clk Trim Value.
-**/
- UINT8 PchSkyCamPortCClkTrimValue;
-
-/** Offset 0x030F - Enable SkyCam PortD Clk Trim Value
- Enable/disable PortD Clk Trim Value.
-**/
- UINT8 PchSkyCamPortDClkTrimValue;
-
-/** Offset 0x0310 - Enable SkyCam Port A Data Trim Value
- Enable/disable Port A Data Trim Value.
-**/
- UINT16 PchSkyCamPortADataTrimValue;
-
-/** Offset 0x0312 - Enable SkyCam Port B Data Trim Value
- Enable/disable Port B Data Trim Value.
-**/
- UINT16 PchSkyCamPortBDataTrimValue;
-
-/** Offset 0x0314 - Enable SkyCam C/D Data Trim Value
- Enable/disable C/D Data Trim Value.
-**/
- UINT16 PchSkyCamPortCDDataTrimValue;
-
-/** Offset 0x0316 - Enable DMI ASPM
- ASPM on PCH side of the DMI Link.
- $EN_DIS
-**/
- UINT8 PchDmiAspm;
-
-/** Offset 0x0317 - Enable Power Optimizer
- Enable DMI Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 PchPwrOptEnable;
-
-/** Offset 0x0318 - PCH Flash Protection Ranges Write Enble
- Write or erase is blocked by hardware.
-**/
- UINT8 PchWriteProtectionEnable[5];
-
-/** Offset 0x031D - PCH Flash Protection Ranges Read Enble
- Read is blocked by hardware.
-**/
- UINT8 PchReadProtectionEnable[5];
-
-/** Offset 0x0322 - PCH Protect Range Limit
- Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
- limit comparison.
-**/
- UINT16 PchProtectedRangeLimit[5];
-
-/** Offset 0x032C - PCH Protect Range Base
- Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
-**/
- UINT16 PchProtectedRangeBase[5];
-
-/** Offset 0x0336 - Enable Pme
- Enable Azalia wake-on-ring.
- $EN_DIS
-**/
- UINT8 PchHdaPme;
-
-/** Offset 0x0337 - IO Buffer Voltage
- I/O Buffer Voltage Mode Select: 0: 3.3V, 1: 1.8V.
-**/
- UINT8 PchHdaIoBufferVoltage;
-
-/** Offset 0x0338 - VC Type
- Virtual Channel Type Select: 0: VC0, 1: VC1.
-**/
- UINT8 PchHdaVcType;
-
-/** Offset 0x0339 - HD Audio Link Frequency
- HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, , 1: 12MHz, 2: 24MHz.
-**/
- UINT8 PchHdaLinkFrequency;
-
-/** Offset 0x033A - iDisp-Link Frequency
- iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
-**/
- UINT8 PchHdaIDispLinkFrequency;
-
-/** Offset 0x033B - iDisp-Link T-mode
- iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 1: 1T.
-**/
- UINT8 PchHdaIDispLinkTmode;
-
-/** Offset 0x033C - Universal Audio Architecture compliance for DSP enabled system
- 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
- driver or SST driver supported).
- $EN_DIS
-**/
- UINT8 PchHdaDspUaaCompliance;
-
-/** Offset 0x033D - iDisplay Audio Codec disconnection
- 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
- $EN_DIS
-**/
- UINT8 PchHdaIDispCodecDisconnect;
-
-/** Offset 0x033E - DSP DMIC Select (PCH_HDAUDIO_DMIC_TYPE enum)
- 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array.
-**/
- UINT8 PchHdaDspEndpointDmic;
-
-/** Offset 0x033F - DSP Bluetooth enablement
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchHdaDspEndpointBluetooth;
-
-/** Offset 0x0340 - Bitmask of supported DSP features
- [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT Intel HFP; [BIT6]
- - BT Intel A2DP; [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0:
- Intel WoV, 1: Windows Voice Activation.
-**/
- UINT32 PchHdaDspFeatureMask;
-
-/** Offset 0x0344 - Bitmask of supported DSP Pre/Post-Processing Modules
- Deprecated: Specific pre/post-processing module bit position must be coherent with
- the ACPI implementation: \_SB.PCI0.HDAS._DSM Function 3: Query Pre/Post Processing
- Module Support.
-**/
- UINT32 PchHdaDspPpModuleMask;
-
-/** Offset 0x0348 - DSP I2S enablement
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchHdaDspEndpointI2s;
-
-/** Offset 0x0349 - Enable PCH Io Apic
- Set to 1 if BDF value is valid.
- $EN_DIS
-**/
- UINT8 PchIoApicBdfValid;
-
-/** Offset 0x034A - PCH Io Apic Bus Number
- Bus/Device/Function used as Requestor / Completer ID. Default is 0xF0.
-**/
- UINT8 PchIoApicBusNumber;
-
-/** Offset 0x034B - PCH Io Apic Device Number
- Bus/Device/Function used as Requestor / Completer ID. Default is 0x1F.
-**/
- UINT8 PchIoApicDeviceNumber;
-
-/** Offset 0x034C - PCH Io Apic Function Number
- Bus/Device/Function used as Requestor / Completer ID. Default is 0x00.
-**/
- UINT8 PchIoApicFunctionNumber;
-
-/** Offset 0x034D - Enable PCH Io Apic Entry 24-119
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIoApicEntry24_119;
-
-/** Offset 0x034E - PCH Io Apic ID
- This member determines IOAPIC ID. Default is 0x02.
-**/
- UINT8 PchIoApicId;
-
-/** Offset 0x034F - PCH Io Apic Range Select
- Define address bits 19:12 for the IOxAPIC range. Default is 0.
-**/
- UINT8 PchIoApicRangeSelect;
-
-/** Offset 0x0350 - Enable PCH ISH SPI GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshSpiGpioAssign;
-
-/** Offset 0x0351 - Enable PCH ISH UART0 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshUart0GpioAssign;
-
-/** Offset 0x0352 - Enable PCH ISH UART1 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshUart1GpioAssign;
-
-/** Offset 0x0353 - Enable PCH ISH I2C0 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshI2c0GpioAssign;
-
-/** Offset 0x0354 - Enable PCH ISH I2C1 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshI2c1GpioAssign;
-
-/** Offset 0x0355 - Enable PCH ISH I2C2 GPIO pins assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshI2c2GpioAssign;
-
-/** Offset 0x0356 - Enable PCH ISH GP_0 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp0GpioAssign;
-
-/** Offset 0x0357 - Enable PCH ISH GP_1 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp1GpioAssign;
-
-/** Offset 0x0358 - Enable PCH ISH GP_2 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp2GpioAssign;
-
-/** Offset 0x0359 - Enable PCH ISH GP_3 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp3GpioAssign;
-
-/** Offset 0x035A - Enable PCH ISH GP_4 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp4GpioAssign;
-
-/** Offset 0x035B - Enable PCH ISH GP_5 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp5GpioAssign;
-
-/** Offset 0x035C - Enable PCH ISH GP_6 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp6GpioAssign;
-
-/** Offset 0x035D - Enable PCH ISH GP_7 GPIO pin assigned
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchIshGp7GpioAssign;
-
-/** Offset 0x035E - PCH ISH PDT Unlock Msg
- 0: False; 1: True.
- $EN_DIS
-**/
- UINT8 PchIshPdtUnlock;
-
-/** Offset 0x035F - Enable PCH Lan LTR capabilty of PCH internal LAN
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchLanLtrEnable;
-
-/** Offset 0x0360 - Enable PCH Lan use CLKREQ for GbE power management
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchLanK1OffEnable;
-
-/** Offset 0x0361 - Indicate whether dedicated CLKREQ# is supported
- 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchLanClkReqSupported;
-
-/** Offset 0x0362 - CLKREQ# used by GbE
- Valid if ClkReqSupported is TRUE.
-**/
- UINT8 PchLanClkReqNumber;
-
-/** Offset 0x0363 - Enable LOCKDOWN BIOS LOCK
- Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
- protection.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosLock;
-
-/** Offset 0x0364 - Enable LOCKDOWN SPI Eiss
- Enable InSMM.STS (EISS) in SPI.
- $EN_DIS
-**/
- UINT8 PchLockDownSpiEiss;
-
-/** Offset 0x0365 - PCH Compatibility Revision ID
- This member describes whether or not the CRID feature of PCH should be enabled.
- $EN_DIS
-**/
- UINT8 PchCrid;
-
-/** Offset 0x0366 - PCH Sub system vendor ID
- Default Subsystem Vendor ID of the PCH devices. Default is 0x8086.
-**/
- UINT16 PchSubSystemVendorId;
-
-/** Offset 0x0368 - PCH Sub system ID
- Default Subsystem ID of the PCH devices. Default is 0x7270.
-**/
- UINT16 PchSubSystemId;
-
-/** Offset 0x036A - PCH Legacy IO Low Latency Enable
- todo
- $EN_DIS
-**/
- UINT8 PchLegacyIoLowLatency;
-
-/** Offset 0x036B
-**/
- UINT8 UnusedUpdSpace15[5];
-
-/** Offset 0x0370 - Enable PCIE RP HotPlug
- Indicate whether the root port is hot plug available.
-**/
- UINT8 PcieRpHotPlug[24];
-
-/** Offset 0x0388 - Enable PCIE RP Pm Sci
- Indicate whether the root port power manager SCI is enabled.
-**/
- UINT8 PcieRpPmSci[24];
-
-/** Offset 0x03A0 - Enable PCIE RP Ext Sync
- Indicate whether the extended synch is enabled.
-**/
- UINT8 PcieRpExtSync[24];
-
-/** Offset 0x03B8 - Enable PCIE RP Transmitter Half Swing
- Indicate whether the Transmitter Half Swing is enabled.
-**/
- UINT8 PcieRpTransmitterHalfSwing[24];
-
-/** Offset 0x03D0 - Enable PCIE RP Clk Req Detect
- Probe CLKREQ# signal before enabling CLKREQ# based power management.
-**/
- UINT8 PcieRpClkReqDetect[24];
-
-/** Offset 0x03E8 - PCIE RP Advanced Error Report
- Indicate whether the Advanced Error Reporting is enabled.
-**/
- UINT8 PcieRpAdvancedErrorReporting[24];
-
-/** Offset 0x0400 - PCIE RP Unsupported Request Report
- Indicate whether the Unsupported Request Report is enabled.
-**/
- UINT8 PcieRpUnsupportedRequestReport[24];
-
-/** Offset 0x0418 - PCIE RP Fatal Error Report
- Indicate whether the Fatal Error Report is enabled.
-**/
- UINT8 PcieRpFatalErrorReport[24];
-
-/** Offset 0x0430 - PCIE RP No Fatal Error Report
- Indicate whether the No Fatal Error Report is enabled.
-**/
- UINT8 PcieRpNoFatalErrorReport[24];
-
-/** Offset 0x0448 - PCIE RP Correctable Error Report
- Indicate whether the Correctable Error Report is enabled.
-**/
- UINT8 PcieRpCorrectableErrorReport[24];
-
-/** Offset 0x0460 - PCIE RP System Error On Fatal Error
- Indicate whether the System Error on Fatal Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnFatalError[24];
-
-/** Offset 0x0478 - PCIE RP System Error On Non Fatal Error
- Indicate whether the System Error on Non Fatal Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnNonFatalError[24];
-
-/** Offset 0x0490 - PCIE RP System Error On Correctable Error
- Indicate whether the System Error on Correctable Error is enabled.
-**/
- UINT8 PcieRpSystemErrorOnCorrectableError[24];
-
-/** Offset 0x04A8 - PCIE RP Max Payload
- Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
-**/
- UINT8 PcieRpMaxPayload[24];
-
-/** Offset 0x04C0 - PCIE RP Device Reset Pad Active High
- Indicated whether PERST# is active 0: Low; 1: High, See: DeviceResetPad.
-**/
- UINT8 PcieRpDeviceResetPadActiveHigh[24];
-
-/** Offset 0x04D8 - PCIE RP Pcie Speed
- Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
- PCH_PCIE_SPEED).
-**/
- UINT8 PcieRpPcieSpeed[24];
-
-/** Offset 0x04F0 - PCIE RP Gen3 Equalization Phase Method
- PCIe Gen3 Eq Ph3 Method (see PCH_PCIE_EQ_METHOD). 0: Default; 2: Software Search;
- 4: Fixed Coeficients.
-**/
- UINT8 PcieRpGen3EqPh3Method[24];
-
-/** Offset 0x0508 - PCIE RP Physical Slot Number
- Indicates the slot number for the root port. Default is the value as root port index.
-**/
- UINT8 PcieRpPhysicalSlotNumber[24];
-
-/** Offset 0x0520 - PCIE RP Completion Timeout
- The root port completion timeout(see: PCH_PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
-**/
- UINT8 PcieRpCompletionTimeout[24];
-
-/** Offset 0x0538 - PCIE RP Device Reset Pad
- The PCH pin assigned to device PERST# signal if available, zero otherwise. See
- also DeviceResetPadActiveHigh.
-**/
- UINT32 PcieRpDeviceResetPad[24];
-
-/** Offset 0x0598 - PCIE RP Aspm
- The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
- PchPcieAspmAutoConfig.
-**/
- UINT8 PcieRpAspm[24];
-
-/** Offset 0x05B0 - PCIE RP L1 Substates
- The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
- Default is PchPcieL1SubstatesL1_1_2.
-**/
- UINT8 PcieRpL1Substates[24];
-
-/** Offset 0x05C8 - PCIE RP Ltr Enable
- Latency Tolerance Reporting Mechanism.
-**/
- UINT8 PcieRpLtrEnable[24];
-
-/** Offset 0x05E0 - PCIE RP Ltr Config Lock
- 0: Disable; 1: Enable.
-**/
- UINT8 PcieRpLtrConfigLock[24];
-
-/** Offset 0x05F8 - PCIE Eq Ph3 Lane Param Cm
- PCH_PCIE_EQ_LANE_PARAM. Coefficient C-1.
-**/
- UINT8 PcieEqPh3LaneParamCm[24];
-
-/** Offset 0x0610 - PCIE Eq Ph3 Lane Param Cp
- PCH_PCIE_EQ_LANE_PARAM. Coefficient C+1.
-**/
- UINT8 PcieEqPh3LaneParamCp[24];
-
-/** Offset 0x0628 - PCIE Sw Eq CoeffList Cm
- PCH_PCIE_EQ_PARAM. Coefficient C-1.
-**/
- UINT8 PcieSwEqCoeffListCm[5];
-
-/** Offset 0x062D - PCIE Sw Eq CoeffList Cp
- PCH_PCIE_EQ_PARAM. Coefficient C+1.
-**/
- UINT8 PcieSwEqCoeffListCp[5];
-
-/** Offset 0x0632 - PCIE Disable RootPort Clock Gating
- Describes whether the PCI Express Clock Gating for each root port is enabled by
- platform modules. 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PcieDisableRootPortClockGating;
-
-/** Offset 0x0633 - PCIE Enable Peer Memory Write
- This member describes whether Peer Memory Writes are enabled on the platform.
- $EN_DIS
-**/
- UINT8 PcieEnablePeerMemoryWrite;
-
-/** Offset 0x0634 - PCIE Allow No Ltr Icc PLL Shutdown
- Allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable
- or leaving untouched.
- $EN_DIS
-**/
- UINT8 PcieAllowNoLtrIccPllShutdown;
-
-/** Offset 0x0635 - PCIE Compliance Test Mode
- Compliance Test Mode shall be enabled when using Compliance Load Board.
- $EN_DIS
-**/
- UINT8 PcieComplianceTestMode;
-
-/** Offset 0x0636 - PCIE Rp Detect Timeout Ms
- Will wait for link to exit Detect state for enabled ports before assuming there
- is no device and potentially disabling the port.
-**/
- UINT16 PcieDetectTimeoutMs;
-
-/** Offset 0x0638 - PCIE Rp Function Swap
- Allows BIOS to use root port function number swapping when root port of function
- 0 is disabled.
- $EN_DIS
-**/
- UINT8 PcieRpFunctionSwap;
-
-/** Offset 0x0639 - PCH Pm PME_B0_S5_DIS
- When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
- $EN_DIS
-**/
- UINT8 PchPmPmeB0S5Dis;
-
-/** Offset 0x063A - PCH Pm Slp S0 Voltage Margining Enable
- Indicates platform has support for VCCPrim_Core Voltage Margining in SLP_S0# asserted state.
- $EN_DIS
-**/
- UINT8 PchPmSlpS0VmEnable;
-
-/** Offset 0x063B
-**/
- UINT8 UnusedUpdSpace16[5];
-
-/** Offset 0x0640 - PCH Pm Wol Enable Override
- Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
- $EN_DIS
-**/
- UINT8 PchPmWolEnableOverride;
-
-/** Offset 0x0641 - PCH Pm Pcie Wake From DeepSx
- Determine if enable PCIe to wake from deep Sx.
- $EN_DIS
-**/
- UINT8 PchPmPcieWakeFromDeepSx;
-
-/** Offset 0x0642 - PCH Pm WoW lan Enable
- Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
- $EN_DIS
-**/
- UINT8 PchPmWoWlanEnable;
-
-/** Offset 0x0643 - PCH Pm WoW lan DeepSx Enable
- Determine if WLAN wake from DeepSx, corresponds to the DSX_WLAN_PP_EN bit in the
- PWRM_CFG3 register.
- $EN_DIS
-**/
- UINT8 PchPmWoWlanDeepSxEnable;
-
-/** Offset 0x0644 - PCH Pm Lan Wake From DeepSx
- Determine if enable LAN to wake from deep Sx.
- $EN_DIS
-**/
- UINT8 PchPmLanWakeFromDeepSx;
-
-/** Offset 0x0645 - PCH Pm Deep Sx Pol
- Deep Sx Policy.
- $EN_DIS
-**/
- UINT8 PchPmDeepSxPol;
-
-/** Offset 0x0646 - PCH Pm Slp S3 Min Assert
- SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
-**/
- UINT8 PchPmSlpS3MinAssert;
-
-/** Offset 0x0647 - PCH Pm Slp S4 Min Assert
- SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
-**/
- UINT8 PchPmSlpS4MinAssert;
-
-/** Offset 0x0648 - PCH Pm Slp Sus Min Assert
- SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
-**/
- UINT8 PchPmSlpSusMinAssert;
-
-/** Offset 0x0649 - PCH Pm Slp A Min Assert
- SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
-**/
- UINT8 PchPmSlpAMinAssert;
-
-/** Offset 0x064A
-**/
- UINT8 UnusedUpdSpace17[6];
-
-/** Offset 0x0650 - PCH Pm Lpc Clock Run
- This member describes whether or not the LPC ClockRun feature of PCH should be enabled.
- $EN_DIS
-**/
- UINT8 PchPmLpcClockRun;
-
-/** Offset 0x0651 - PCH Pm Slp Strch Sus Up
- Enable SLP_X Stretching After SUS Well Power Up.
- $EN_DIS
-**/
- UINT8 PchPmSlpStrchSusUp;
-
-/** Offset 0x0652 - PCH Pm Slp Lan Low Dc
- Enable/Disable SLP_LAN# Low on DC Power.
- $EN_DIS
-**/
- UINT8 PchPmSlpLanLowDc;
-
-/** Offset 0x0653 - PCH Pm Pwr Btn Override Period
- PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
-**/
- UINT8 PchPmPwrBtnOverridePeriod;
-
-/** Offset 0x0654 - PCH Pm Disable Dsx Ac Present Pulldown
- When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
- $EN_DIS
-**/
- UINT8 PchPmDisableDsxAcPresentPulldown;
-
-/** Offset 0x0655 - PCH Pm Capsule Reset Type
- Deprecated: Determines type of reset issued during UpdateCapsule(). Always Warm reset.
- $EN_DIS
-**/
- UINT8 PchPmCapsuleResetType;
-
-/** Offset 0x0656 - PCH Pm Disable Native Power Button
- Power button native mode disable.
- $EN_DIS
-**/
- UINT8 PchPmDisableNativePowerButton;
-
-/** Offset 0x0657 - PCH Pm Slp S0 Enable
- Indicates whether SLP_S0# is to be asserted when PCH reaches idle state.
- $EN_DIS
-**/
- UINT8 PchPmSlpS0Enable;
-
-/** Offset 0x0658 - PCH Pm ME_WAKE_STS
- Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
- $EN_DIS
-**/
- UINT8 PchPmMeWakeSts;
-
-/** Offset 0x0659 - PCH Pm WOL_OVR_WK_STS
- Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
- $EN_DIS
-**/
- UINT8 PchPmWolOvrWkSts;
-
-/** Offset 0x065A - PCH Pm Reset Power Cycle Duration
- Could be customized in the unit of second. Please refer to EDS for all support settings.
- 0 is default, 1 is 1 second, 2 is 2 seconds, ...
-**/
- UINT8 PchPmPwrCycDur;
-
-/** Offset 0x065B
-**/
- UINT8 UnusedUpdSpace18;
-
-/** Offset 0x065C - PCH Port 61h Config Enable/Disable
- Used for the emulation feature for Port61h read. The port is trapped and the SMI
- handler will toggle bit4 according to the handler's internal state.
- $EN_DIS
-**/
- UINT8 PchPort61hEnable;
-
-/** Offset 0x065D - PCH Sata Pwr Opt Enable
- SATA Power Optimizer on PCH side.
- $EN_DIS
-**/
- UINT8 SataPwrOptEnable;
-
-/** Offset 0x065E - PCH Sata eSATA Speed Limit
- When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
- $EN_DIS
-**/
- UINT8 EsataSpeedLimit;
-
-/** Offset 0x065F - PCH Sata Speed Limit
- Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
-**/
- UINT8 SataSpeedLimit;
-
-/** Offset 0x0660 - Enable SATA Port HotPlug
- Enable SATA Port HotPlug.
-**/
- UINT8 SataPortsHotPlug[8];
-
-/** Offset 0x0668 - Enable SATA Port Interlock Sw
- Enable SATA Port Interlock Sw.
-**/
- UINT8 SataPortsInterlockSw[8];
-
-/** Offset 0x0670 - Enable SATA Port External
- Enable SATA Port External.
-**/
- UINT8 SataPortsExternal[8];
-
-/** Offset 0x0678 - Enable SATA Port SpinUp
- Enable the COMRESET initialization Sequence to the device.
-**/
- UINT8 SataPortsSpinUp[8];
-
-/** Offset 0x0680 - Enable SATA Port Solid State Drive
- 0: HDD; 1: SSD.
-**/
- UINT8 SataPortsSolidStateDrive[8];
-
-/** Offset 0x0688 - Enable SATA Port Enable Dito Config
- Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
-**/
- UINT8 SataPortsEnableDitoConfig[8];
-
-/** Offset 0x0690 - Enable SATA Port DmVal
- DITO multiplier. Default is 15.
-**/
- UINT8 SataPortsDmVal[8];
-
-/** Offset 0x0698 - Enable SATA Port DmVal
- DEVSLP Idle Timeout (DITO), Default is 625.
-**/
- UINT16 SataPortsDitoVal[8];
-
-/** Offset 0x06A8 - Enable SATA Port ZpOdd
- Support zero power ODD.
-**/
- UINT8 SataPortsZpOdd[8];
-
-/** Offset 0x06B0 - PCH Sata Rst Raid Alternate Id
- Enable RAID Alternate ID.
- 0:Client, 1:Alternate, 2:Server
-**/
- UINT8 SataRstRaidAlternateId;
-
-/** Offset 0x06B1 - PCH Sata Rst Raid0
- RAID0.
- $EN_DIS
-**/
- UINT8 SataRstRaid0;
-
-/** Offset 0x06B2 - PCH Sata Rst Raid1
- RAID1.
- $EN_DIS
-**/
- UINT8 SataRstRaid1;
-
-/** Offset 0x06B3 - PCH Sata Rst Raid10
- RAID10.
- $EN_DIS
-**/
- UINT8 SataRstRaid10;
-
-/** Offset 0x06B4 - PCH Sata Rst Raid5
- RAID5.
- $EN_DIS
-**/
- UINT8 SataRstRaid5;
-
-/** Offset 0x06B5 - PCH Sata Rst Irrt
- Intel Rapid Recovery Technology.
- $EN_DIS
-**/
- UINT8 SataRstIrrt;
-
-/** Offset 0x06B6 - PCH Sata Rst Orom Ui Banner
- OROM UI and BANNER.
- $EN_DIS
-**/
- UINT8 SataRstOromUiBanner;
-
-/** Offset 0x06B7 - PCH Sata Rst Orom Ui Delay
- 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
-**/
- UINT8 SataRstOromUiDelay;
-
-/** Offset 0x06B8 - PCH Sata Rst Hdd Unlock
- Indicates that the HDD password unlock in the OS is enabled.
- $EN_DIS
-**/
- UINT8 SataRstHddUnlock;
-
-/** Offset 0x06B9 - PCH Sata Rst Led Locate
- Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
- enabled on the OS.
- $EN_DIS
-**/
- UINT8 SataRstLedLocate;
-
-/** Offset 0x06BA - PCH Sata Rst Irrt Only
- Allow only IRRT drives to span internal and external ports.
- $EN_DIS
-**/
- UINT8 SataRstIrrtOnly;
-
-/** Offset 0x06BB - PCH Sata Rst Smart Storage
- RST Smart Storage caching Bit.
- $EN_DIS
-**/
- UINT8 SataRstSmartStorage;
-
-/** Offset 0x06BC - PCH Sata Rst Pcie Storage Remap enable
- Enable Intel RST for PCIe Storage remapping.
-**/
- UINT8 SataRstPcieEnable[3];
-
-/** Offset 0x06BF - PCH Sata Rst Pcie Storage Port
- Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
-**/
- UINT8 SataRstPcieStoragePort[3];
-
-/** Offset 0x06C2 - PCH Sata Rst Pcie Device Reset Delay
- PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
-**/
- UINT8 SataRstPcieDeviceResetDelay[3];
-
-/** Offset 0x06C5 - Enable eMMC HS400 Training
- Determine if HS400 Training is required.
- $EN_DIS
-**/
- UINT8 PchScsEmmcHs400TuningRequired;
-
-/** Offset 0x06C6 - Set HS400 Tuning Data Valid
- Set if HS400 Tuning Data Valid.
- $EN_DIS
-**/
- UINT8 PchScsEmmcHs400DllDataValid;
-
-/** Offset 0x06C7 - Rx Strobe Delay Control
- Rx Strobe Delay Control - Rx Strobe Delay DLL 1 (HS400 Mode).
-**/
- UINT8 PchScsEmmcHs400RxStrobeDll1;
-
-/** Offset 0x06C8 - Tx Data Delay Control
- Tx Data Delay Control 1 - Tx Data Delay (HS400 Mode).
-**/
- UINT8 PchScsEmmcHs400TxDataDll;
-
-/** Offset 0x06C9 - I/O Driver Strength
- I/O driver strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm.
-**/
- UINT8 PchScsEmmcHs400DriverStrength;
-
-/** Offset 0x06CA - Enable Pch Serial IO GPIO
- Determines if enable Serial IO GPIO.
- $EN_DIS
-**/
- UINT8 SerialIoGpio;
-
-/** Offset 0x06CB - IO voltage for I2C controllers
- Selects the IO voltage for I2C controllers, 0: PchSerialIoIs33V, 1: PchSerialIoIs18V.
-**/
- UINT8 SerialIoI2cVoltage[6];
-
-/** Offset 0x06D1 - SPI ChipSelect signal polarity
- Selects SPI ChipSelect signal polarity.
-**/
- UINT8 SerialIoSpiCsPolarity[2];
-
-/** Offset 0x06D3 - Enables UART hardware flow control, CTS and RTS lines
- Enables UART hardware flow control, CTS and RTS linesh.
-**/
- UINT8 SerialIoUartHwFlowCtrl[3];
-
-/** Offset 0x06D6 - UART Number For Debug Purpose
- UART number for debug purpose. 0:UART0, 1: UART1, 2:UART2.
-**/
- UINT8 SerialIoDebugUartNumber;
-
-/** Offset 0x06D7 - Enable Debug UART Controller
- Enable debug UART controller after post.
-**/
- UINT8 SerialIoEnableDebugUartAfterPost;
-
-/** Offset 0x06D8 - Enable Serial IRQ
- Determines if enable Serial IRQ.
- $EN_DIS
-**/
- UINT8 PchSirqEnable;
-
-/** Offset 0x06D9 - Serial IRQ Mode Select
- Serial IRQ Mode Select, 0: quiet mode, 1: continuous mode.
- $EN_DIS
-**/
- UINT8 PchSirqMode;
-
-/** Offset 0x06DA - Start Frame Pulse Width
- Start Frame Pulse Width, 0: PchSfpw4Clk, 1: PchSfpw6Clk, 2: PchSfpw8Clk.
-**/
- UINT8 PchStartFramePulse;
-
-/** Offset 0x06DB - Enable Thermal Device
- Enable Thermal Device.
- $EN_DIS
-**/
- UINT8 PchThermalDeviceEnable;
-
-/** Offset 0x06DC - Thermal Throttling Custimized T0Level Value
- Custimized T0Level value.
-**/
- UINT16 PchT0Level;
-
-/** Offset 0x06DE - Thermal Throttling Custimized T1Level Value
- Custimized T1Level value.
-**/
- UINT16 PchT1Level;
-
-/** Offset 0x06E0 - Thermal Throttling Custimized T2Level Value
- Custimized T2Level value.
-**/
- UINT16 PchT2Level;
-
-/** Offset 0x06E2 - Thermal Device SMI Enable
- This locks down SMI Enable on Alert Thermal Sensor Trip.
- $EN_DIS
-**/
- UINT8 PchTsmicLock;
-
-/** Offset 0x06E3 - Enable The Thermal Throttle
- Enable the thermal throttle function.
- $EN_DIS
-**/
- UINT8 PchTTEnable;
-
-/** Offset 0x06E4 - PMSync State 13
- When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
- at least T2 state.
- $EN_DIS
-**/
- UINT8 PchTTState13Enable;
-
-/** Offset 0x06E5 - Thermal Throttle Lock
- Thermal Throttle Lock.
- $EN_DIS
-**/
- UINT8 PchTTLock;
-
-/** Offset 0x06E6 - Thermal Throttling Suggested Setting
- Thermal Throttling Suggested Setting.
- $EN_DIS
-**/
- UINT8 TTSuggestedSetting;
-
-/** Offset 0x06E7 - Enable PCH Cross Throttling
- Enable/Disable PCH Cross Throttling
- $EN_DIS
-**/
- UINT8 TTCrossThrottling;
-
-/** Offset 0x06E8 - DMI Thermal Sensor Autonomous Width Enable
- DMI Thermal Sensor Autonomous Width Enable.
- $EN_DIS
-**/
- UINT8 PchDmiTsawEn;
-
-/** Offset 0x06E9 - DMI Thermal Sensor Suggested Setting
- DMT thermal sensor suggested representative values.
- $EN_DIS
-**/
- UINT8 DmiSuggestedSetting;
-
-/** Offset 0x06EA - Thermal Sensor 0 Target Width
- Thermal Sensor 0 Target Width.
-**/
- UINT8 DmiTS0TW;
-
-/** Offset 0x06EB - Thermal Sensor 1 Target Width
- Thermal Sensor 1 Target Width.
-**/
- UINT8 DmiTS1TW;
-
-/** Offset 0x06EC - Thermal Sensor 2 Target Width
- Thermal Sensor 2 Target Width.
-**/
- UINT8 DmiTS2TW;
-
-/** Offset 0x06ED - Thermal Sensor 3 Target Width
- Thermal Sensor 3 Target Width.
-**/
- UINT8 DmiTS3TW;
-
-/** Offset 0x06EE - Port 0 T1 Multipler
- Port 0 T1 Multipler.
-**/
- UINT8 SataP0T1M;
-
-/** Offset 0x06EF - Port 0 T2 Multipler
- Port 0 T2 Multipler.
-**/
- UINT8 SataP0T2M;
-
-/** Offset 0x06F0 - Port 0 T3 Multipler
- Port 0 T3 Multipler.
-**/
- UINT8 SataP0T3M;
-
-/** Offset 0x06F1 - Port 0 Tdispatch
- Port 0 Tdispatch.
-**/
- UINT8 SataP0TDisp;
-
-/** Offset 0x06F2 - Port 1 T1 Multipler
- Port 1 T1 Multipler.
-**/
- UINT8 SataP1T1M;
-
-/** Offset 0x06F3 - Port 1 T2 Multipler
- Port 1 T2 Multipler.
-**/
- UINT8 SataP1T2M;
-
-/** Offset 0x06F4 - Port 1 T3 Multipler
- Port 1 T3 Multipler.
-**/
- UINT8 SataP1T3M;
-
-/** Offset 0x06F5 - Port 1 Tdispatch
- Port 1 Tdispatch.
-**/
- UINT8 SataP1TDisp;
-
-/** Offset 0x06F6 - Port 0 Tinactive
- Port 0 Tinactive.
-**/
- UINT8 SataP0Tinact;
-
-/** Offset 0x06F7 - Port 0 Alternate Fast Init Tdispatch
- Port 0 Alternate Fast Init Tdispatch.
- $EN_DIS
-**/
- UINT8 SataP0TDispFinit;
-
-/** Offset 0x06F8 - Port 1 Tinactive
- Port 1 Tinactive.
-**/
- UINT8 SataP1Tinact;
-
-/** Offset 0x06F9 - Port 1 Alternate Fast Init Tdispatch
- Port 1 Alternate Fast Init Tdispatch.
- $EN_DIS
-**/
- UINT8 SataP1TDispFinit;
-
-/** Offset 0x06FA - Sata Thermal Throttling Suggested Setting
- Sata Thermal Throttling Suggested Setting.
- $EN_DIS
-**/
- UINT8 SataThermalSuggestedSetting;
-
-/** Offset 0x06FB - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
- $EN_DIS
-**/
- UINT8 PchMemoryThrottlingEnable;
-
-/** Offset 0x06FC - Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryPmsyncEnable[2];
-
-/** Offset 0x06FE - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryC0TransmitEnable[2];
-
-/** Offset 0x0700 - Enable Memory Thermal Throttling
- Enable Memory Thermal Throttling.
-**/
- UINT8 PchMemoryPinSelection[2];
-
-/** Offset 0x0702 - Thermal Device Temperature
- Decides the temperature.
-**/
- UINT16 PchTemperatureHotLevel;
-
-/** Offset 0x0704 - Disable XHCI Compliance Mode
- This policy will disable XHCI compliance mode on all ports. Complicance Mode should
- be default enabled.
- $EN_DIS
-**/
- UINT8 PchDisableComplianceMode;
-
-/** Offset 0x0705 - USB2 Port Over Current Pin
- Describe the specific over current pin number of USB 2.0 Port N.
-**/
- UINT8 Usb2OverCurrentPin[16];
-
-/** Offset 0x0715 - USB3 Port Over Current Pin
- Describe the specific over current pin number of USB 3.0 Port N.
-**/
- UINT8 Usb3OverCurrentPin[10];
-
-/** Offset 0x071F - Enable 8254 Static Clock Gating in early POST time
- Set 8254CGE=1 is required for C11 support. However, set 8254CGE=1 in POST time might
- fail to boot legacy OS which using 8254 timer. Make sure it won't break legacy
- OS boot before enabling this.
- $EN_DIS
-**/
- UINT8 Early8254ClockGatingEnable;
-
-/** Offset 0x0720 - PCH Sata Rst Optane Memory
- Optane Memory
- $EN_DIS
-**/
- UINT8 SataRstOptaneMemory;
-
-/** Offset 0x0721
-**/
- UINT8 UnusedUpdSpace19[3];
-
-/** Offset 0x0724 - Pch PCIE device override table pointer
- The PCIe device table is being used to override PCIe device ASPM settings. This
- is a pointer points to a 32bit address. And it's only used in PostMem phase. Please
- refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. Last entry VendorId
- must be 0.
-**/
- UINT32 PchPcieDeviceOverrideTablePtr;
-
-/** Offset 0x0728 - Enable TCO timer.
- When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
- huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
- emulation must be enabled, and WDAT table must not be exposed to the OS.
- $EN_DIS
-**/
- UINT8 EnableTcoTimer;
-
-/** Offset 0x0729 - EcCmdProvisionEav
- Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
-**/
- UINT8 EcCmdProvisionEav;
-
-/** Offset 0x072A - EcCmdLock
- EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
-**/
- UINT8 EcCmdLock;
-
-/** Offset 0x072B
-**/
- UINT8 UnusedUpdSpace20[5];
-
-/** Offset 0x0730 - SendEcCmd
- SendEcCmd function pointer. \n
- @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
- EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
-**/
- UINT64 SendEcCmd;
-
-/** Offset 0x0738 - BgpdtHash[4]
- BgpdtHash values
-**/
- UINT64 BgpdtHash[4];
-
-/** Offset 0x0758 - BiosGuardModulePtr
- BiosGuardModulePtr default values
-**/
- UINT64 BiosGuardModulePtr;
-
-/** Offset 0x0760 - BiosGuardAttr
- BiosGuardAttr default values
-**/
- UINT32 BiosGuardAttr;
-
-/** Offset 0x0764 - SgxSinitNvsData
- SgxSinitNvsData default values
-**/
- UINT8 SgxSinitNvsData;
-
-/** Offset 0x0765
-**/
- UINT8 UnusedUpdSpace21[3];
-
-/** Offset 0x0768 - SgxEpoch0
- SgxEpoch0 default values
-**/
- UINT64 SgxEpoch0;
-
-/** Offset 0x0770 - SgxEpoch1
- SgxEpoch1 default values
-**/
- UINT64 SgxEpoch1;
-
-/** Offset 0x0778 - Enable/Disable ME Unconfig on RTC clear
- Enable(Default): Enable ME Unconfig On Rtc Clear, Disable: Disable ME Unconfig On Rtc Clear
- $EN_DIS
-**/
- UINT8 MeUnconfigOnRtcClear;
-
-/** Offset 0x0779 - Check if MeUnconfigOnRtcClear is valid
- The MeUnconfigOnRtcClear item could be not valid due to CMOS is clear.
- $EN_DIS
-**/
- UINT8 MeUnconfigIsValid;
-
-/** Offset 0x077A - Activates VR mailbox command for Intersil VR C-state issues.
- Intersil VR mailbox command. <b>0 - no mailbox command sent.</b> 1 - VR mailbox
- command sent for IA/GT rails only. 2 - VR mailbox command sent for IA/GT/SA rails.
-**/
- UINT8 IslVrCmd;
-
-/** Offset 0x077B
-**/
- UINT8 ReservedFspsUpd[5];
-} FSP_S_CONFIG;
-
-/** Fsp S Test Configuration
-**/
-typedef struct {
-
-/** Offset 0x0780
-**/
- UINT32 Signature;
-
-/** Offset 0x0784 - Enable/Disable Device 7
- Enable: Device 7 enabled, Disable (Default): Device 7 disabled
- $EN_DIS
-**/
- UINT8 ChapDeviceEnable;
-
-/** Offset 0x0785 - Skip PAM register lock
- Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
- PAM registers will be locked by RC
- $EN_DIS
-**/
- UINT8 SkipPamLock;
-
-/** Offset 0x0786 - EDRAM Test Mode
- Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
- PAM registers will be locked by RC
- 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
-**/
- UINT8 EdramTestMode;
-
-/** Offset 0x0787 - DMI Extended Sync Control
- Enable: Enable DMI Extended Sync Control, Disable(Default): Disable DMI Extended
- Sync Control
- $EN_DIS
-**/
- UINT8 DmiExtSync;
-
-/** Offset 0x0788 - DMI IOT Control
- Enable: Enable DMI IOT Control, Disable(Default): Disable DMI IOT Control
- $EN_DIS
-**/
- UINT8 DmiIot;
-
-/** Offset 0x0789 - PEG Max Payload size per root port
- 0xFF(Default):Auto, 0x1: Force 128B, 0x2: Force 256B
- 0xFF: Auto, 0x1: Force 128B, 0x2: Force 256B
-**/
- UINT8 PegMaxPayload[3];
-
-/** Offset 0x078C - Enable/Disable IGFX RenderStandby
- Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
- $EN_DIS
-**/
- UINT8 RenderStandby;
-
-/** Offset 0x078D - Enable/Disable IGFX PmSupport
- Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
- $EN_DIS
-**/
- UINT8 PmSupport;
-
-/** Offset 0x078E - Enable/Disable CdynmaxClamp
- Enable(Default): Enable CdynmaxClamp, Disable: Disable CdynmaxClamp
- $EN_DIS
-**/
- UINT8 CdynmaxClampEnable;
-
-/** Offset 0x078F - Disable VT-d
- 0=Enable/FALSE(VT-d disabled), 1=Disable/TRUE (VT-d enabled)
- $EN_DIS
-**/
- UINT8 VtdDisable;
-
-/** Offset 0x0790 - GT Frequency Limit
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
- 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
- 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
- 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
- 0x13: 950 Mhz, 0x14: 1000 Mhz, 0x15: 1050 Mhz, 0x16: 1100 Mhz, 0x17: 1150 Mhz,
- 0x18: 1200 Mhz
-**/
- UINT8 GtFreqMax;
-
-/** Offset 0x0791 - SaPostMemTestRsvd
- Reserved for SA Post-Mem Test
- $EN_DIS
-**/
- UINT8 SaPostMemTestRsvd[11];
-
-/** Offset 0x079C - 1-Core Ratio Limit
- 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
- to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit, 5-Core Ratio Limit,
- 6-Core Ratio Limit, 7-Core Ratio Limit, 8-Core Ratio Limit. Range is 0 to 83
-**/
- UINT8 OneCoreRatioLimit;
-
-/** Offset 0x079D - 2-Core Ratio Limit
- 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 TwoCoreRatioLimit;
-
-/** Offset 0x079E - 3-Core Ratio Limit
- 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 ThreeCoreRatioLimit;
-
-/** Offset 0x079F - 4-Core Ratio Limit
- 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 FourCoreRatioLimit;
-
-/** Offset 0x07A0
-**/
- UINT8 UnusedUpdSpace22;
-
-/** Offset 0x07A1 - Enable or Disable HWP
- Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
- 2-3:Reserved
- $EN_DIS
-**/
- UINT8 Hwp;
-
-/** Offset 0x07A2 - Hardware Duty Cycle Control
- Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
- $EN_DIS
-**/
- UINT8 HdcControl;
-
-/** Offset 0x07A3 - Package Long duration turbo mode time
- Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)
- 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
-**/
- UINT8 PowerLimit1Time;
-
-/** Offset 0x07A4 - Short Duration Turbo Mode
- Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 PowerLimit2;
-
-/** Offset 0x07A5 - Turbo settings Lock
- Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
- $EN_DIS
-**/
- UINT8 TurboPowerLimitLock;
-
-/** Offset 0x07A6 - Package PL3 time window
- Package PL3 time window range for this policy in milliseconds. Valid values are
- 0, 3 to 8, 10, 12, 14, 16, 20 , 24, 28, 32, 40, 48, 55, 56, 64
-**/
- UINT8 PowerLimit3Time;
-
-/** Offset 0x07A7 - Package PL3 Duty Cycle
- Package PL3 Duty Cycle; Valid Range is 0 to 100
-**/
- UINT8 PowerLimit3DutyCycle;
-
-/** Offset 0x07A8 - Package PL3 Lock
- Package PL3 Lock Enable/Disable; <b>0: Disable ; <b> 1: Enable
- $EN_DIS
-**/
- UINT8 PowerLimit3Lock;
-
-/** Offset 0x07A9 - Package PL4 Lock
- Package PL4 Lock Enable/Disable; <b>0: Disable ; <b>1: Enable
- $EN_DIS
-**/
- UINT8 PowerLimit4Lock;
-
-/** Offset 0x07AA - TCC Activation Offset
- TCC Activation Offset. Offset from factory set TCC activation temperature at which
- the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
- Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
- <b>10</b>, For all other SKUs the recommended default are <b>0</b>
-**/
- UINT8 TccActivationOffset;
-
-/** Offset 0x07AB - Tcc Offset Clamp Enable/Disable
- Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
- below P1.For SKL Y SKU, the recommended default for this policy is <b>1: Enabled</b>,
- For all other SKUs the recommended default are <b>0: Disabled</b>.
- $EN_DIS
-**/
- UINT8 TccOffsetClamp;
-
-/** Offset 0x07AC - Tcc Offset Lock
- Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
- target; <b>0: Disabled</b>; 1: Enabled.
- $EN_DIS
-**/
- UINT8 TccOffsetLock;
-
-/** Offset 0x07AD - Custom Ratio State Entries
- The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
- ratio table.Sets the number of custom P-states. At least 2 states must be present
-**/
- UINT8 NumberOfEntries;
-
-/** Offset 0x07AE - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128
-**/
- UINT8 Custom1PowerLimit1Time;
-
-/** Offset 0x07AF - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
-**/
- UINT8 Custom1TurboActivationRatio;
-
-/** Offset 0x07B0 - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom1ConfigTdpControl;
-
-/** Offset 0x07B1 - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128
-**/
- UINT8 Custom2PowerLimit1Time;
-
-/** Offset 0x07B2 - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
-**/
- UINT8 Custom2TurboActivationRatio;
-
-/** Offset 0x07B3 - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom2ConfigTdpControl;
-
-/** Offset 0x07B4 - Custom Short term Power Limit time window
- Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128
-**/
- UINT8 Custom3PowerLimit1Time;
-
-/** Offset 0x07B5 - Custom Turbo Activation Ratio
- Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
-**/
- UINT8 Custom3TurboActivationRatio;
-
-/** Offset 0x07B6 - Custom Config Tdp Control
- Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
-**/
- UINT8 Custom3ConfigTdpControl;
-
-/** Offset 0x07B7 - ConfigTdp mode settings Lock
- Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 ConfigTdpLock;
-
-/** Offset 0x07B8 - Load Configurable TDP SSDT
- Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ConfigTdpBios;
-
-/** Offset 0x07B9 - PL1 Enable value
- PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 PsysPowerLimit1;
-
-/** Offset 0x07BA - PL1 timewindow
- PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16
- , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
-**/
- UINT8 PsysPowerLimit1Time;
-
-/** Offset 0x07BB - PL2 Enable Value
- PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
- 1: Enable.
- $EN_DIS
-**/
- UINT8 PsysPowerLimit2;
-
-/** Offset 0x07BC
-**/
- UINT8 UnusedUpdSpace23[2];
-
-/** Offset 0x07BE - Enable or Disable MLC Streamer Prefetcher
- Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MlcStreamerPrefetcher;
-
-/** Offset 0x07BF - Enable or Disable MLC Spatial Prefetcher
- Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 MlcSpatialPrefetcher;
-
-/** Offset 0x07C0 - Enable or Disable Monitor /MWAIT instructions
- Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MonitorMwaitEnable;
-
-/** Offset 0x07C1 - Enable or Disable initialization of machine check registers
- Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 MachineCheckEnable;
-
-/** Offset 0x07C2 - Enable or Disable processor debug features
- Enable or Disable processor debug features; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 DebugInterfaceEnable;
-
-/** Offset 0x07C3 - Lock or Unlock debug interface features
- Lock or Unlock debug interface features; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 DebugInterfaceLockEnable;
-
-/** Offset 0x07C4 - AP Idle Manner of waiting for SIPI
- AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
- 1:HALT loop, 2:MWAIT loop, 3:RUN loop
-**/
- UINT8 ApIdleManner;
-
-/** Offset 0x07C5 - Settings for AP Handoff to OS
- Settings for AP Handoff to OS; 1: HALT loop; <b>2: MWAIT loop</b>.
- 1:HALT loop, 2:MWAIT loop
-**/
- UINT8 ApHandoffManner;
-
-/** Offset 0x07C6
-**/
- UINT8 UnusedUpdSpace24[2];
-
-/** Offset 0x07C8 - Control on Processor Trace output scheme
- Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
- 0:Single Range Output, 1:ToPA Output
-**/
- UINT8 ProcTraceOutputScheme;
-
-/** Offset 0x07C9 - Enable or Disable Processor Trace feature
- Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ProcTraceEnable;
-
-/** Offset 0x07CA - Memory region allocation for Processor Trace
- Memory region allocation for Processor Trace, Total Memory required is up to requested
- value * 2 (for memory alignment) * 8 active threads, to enable Processor Trace,
- PcdFspReservedMemoryLength must be increased by the total memory required, and
- PlatformMemorySize policy must also be increased by the total memory required over
- 32MB, Valid Values are 0 - 4KB , 0x1 - 8KB , 0x2 - 16KB , 0x3 - 32KB , 0x4 - 64KB
- , 0x5 - 128KB , 0x6 - 256KB , 0x7 - 512KB , 0x8 - 1MB , 0x9 - 2MB , 0xA - 4MB ,
- 0xB - 8MB , 0xC - 16MB , 0xD - 32MB , 0xE - 64MB , 0xF - 128MB , 0xFF: Disable
-**/
- UINT8 ProcTraceMemSize;
-
-/** Offset 0x07CB
-**/
- UINT8 UnusedUpdSpace25;
-
-/** Offset 0x07CC - Enable or Disable Voltage Optimization feature
- Enable or Disable Voltage Optimization feature 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 VoltageOptimization;
-
-/** Offset 0x07CD - Enable or Disable Intel SpeedStep Technology
- Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 Eist;
-
-/** Offset 0x07CE - Enable or Disable Energy Efficient P-state
- Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
- <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnergyEfficientPState;
-
-/** Offset 0x07CF - Enable or Disable Energy Efficient Turbo
- Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
- <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 EnergyEfficientTurbo;
-
-/** Offset 0x07D0 - Enable or Disable T states
- Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 TStates;
-
-/** Offset 0x07D1 - Enable or Disable Bi-Directional PROCHOT#
- Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 BiProcHot;
-
-/** Offset 0x07D2 - Enable or Disable PROCHOT# signal being driven externally
- Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 DisableProcHotOut;
-
-/** Offset 0x07D3 - Enable or Disable PROCHOT# Response
- Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 ProcHotResponse;
-
-/** Offset 0x07D4 - Enable or Disable VR Thermal Alert
- Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 DisableVrThermalAlert;
-
-/** Offset 0x07D5 - Enable or Disable Thermal Reporting
- Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 AutoThermalReporting;
-
-/** Offset 0x07D6 - Enable or Disable Thermal Monitor
- Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 ThermalMonitor;
-
-/** Offset 0x07D7 - Enable or Disable CPU power states (C-states)
- Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 Cx;
-
-/** Offset 0x07D8 - Configure C-State Configuration Lock
- Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
- $EN_DIS
-**/
- UINT8 PmgCstCfgCtrlLock;
-
-/** Offset 0x07D9 - Enable or Disable Enhanced C-states
- Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 C1e;
-
-/** Offset 0x07DA - Enable or Disable Package C-State Demotion
- Enable or Disable Package C-State Demotion. 0: Disable; 1: Enable; <b>2: Auto</b>
- (Auto: Enabled for Skylake; Disabled for Kabylake)
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 PkgCStateDemotion;
-
-/** Offset 0x07DB - Enable or Disable Package C-State UnDemotion
- Enable or Disable Package C-State UnDemotion. 0: Disable; 1: Enable; <b>2: Auto</b>
- (Auto: Enabled for Skylake; Disabled for Kabylake)
- 0:Disable, 1:Enable, 2:Auto
-**/
- UINT8 PkgCStateUnDemotion;
-
-/** Offset 0x07DC - Enable or Disable CState-Pre wake
- Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 CStatePreWake;
-
-/** Offset 0x07DD - Enable or Disable TimedMwait Support.
- Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 TimedMwait;
-
-/** Offset 0x07DE - Enable or Disable IO to MWAIT redirection
- Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
- $EN_DIS
-**/
- UINT8 CstCfgCtrIoMwaitRedirection;
-
-/** Offset 0x07DF - Set the Max Pkg Cstate
- Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
- C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
- 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
-**/
- UINT8 PkgCStateLimit;
-
-/** Offset 0x07E0 - TimeUnit for C-State Latency Control0
- TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl0TimeUnit;
-
-/** Offset 0x07E1 - TimeUnit for C-State Latency Control1
- TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl1TimeUnit;
-
-/** Offset 0x07E2 - TimeUnit for C-State Latency Control2
- TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl2TimeUnit;
-
-/** Offset 0x07E3 - TimeUnit for C-State Latency Control3
- TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl3TimeUnit;
-
-/** Offset 0x07E4 - TimeUnit for C-State Latency Control4
- TimeUnit for C-State Latency Control4;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl4TimeUnit;
-
-/** Offset 0x07E5 - TimeUnit for C-State Latency Control5
- TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
- , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
-**/
- UINT8 CstateLatencyControl5TimeUnit;
-
-/** Offset 0x07E6 - Interrupt Redirection Mode Select
- Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;4:
- PAIR with fixed priority;5: PAIR with round robin;6: PAIR with hash vector;7: No change.
-**/
- UINT8 PpmIrmSetting;
-
-/** Offset 0x07E7 - Lock prochot configuration
- Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
- $EN_DIS
-**/
- UINT8 ProcHotLock;
-
-/** Offset 0x07E8 - Configuration for boot TDP selection
- Configuration for boot TDP selection; <b>0: TDP Nominal</b>; 1: TDP Down; 2: TDP
- Up; 0xFF: Deactivate
- 0:TDP Nominal, 1:TDP Down, 2:TDP Up, 0xFF:Deactivate
-**/
- UINT8 ConfigTdpLevel;
-
-/** Offset 0x07E9 - Race To Halt
- Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
- in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
- through MSR 1FC bit 20)Disable; <b>1: Enable</b>
- $EN_DIS
-**/
- UINT8 RaceToHalt;
-
-/** Offset 0x07EA - Max P-State Ratio
- Max P-State Ratio , Valid Range 0 to 0x7F
-**/
- UINT16 MaxRatio;
-
-/** Offset 0x07EC - Maximum P-state ratio to use in the custom P-state table
- Maximum P-state ratio to use in the custom P-state table. NumOfCustomPStates has
- valid range between 0 to 40. For no. of P-States supported(NumOfCustomPStates)
- , StateRatio[NumOfCustomPStates] are configurable. Valid Range of value is 0 to 0x7F
-**/
- UINT16 StateRatio[40];
-
-/** Offset 0x083C - Interrupt Response Time Limit of C-State LatencyContol0
- Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF,
- Default is 0x4E, Server Platform is 0x4B
-**/
- UINT16 CstateLatencyControl0Irtl;
-
-/** Offset 0x083E - Interrupt Response Time Limit of C-State LatencyContol1
- Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF,
- Default is 0x76, Server Platform is 0x6B
-**/
- UINT16 CstateLatencyControl1Irtl;
-
-/** Offset 0x0840 - Interrupt Response Time Limit of C-State LatencyContol2
- Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl2Irtl;
-
-/** Offset 0x0842 - Interrupt Response Time Limit of C-State LatencyContol3
- Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl3Irtl;
-
-/** Offset 0x0844 - Interrupt Response Time Limit of C-State LatencyContol4
- Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl4Irtl;
-
-/** Offset 0x0846 - Interrupt Response Time Limit of C-State LatencyContol5
- Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF
-**/
- UINT16 CstateLatencyControl5Irtl;
-
-/** Offset 0x0848 - Package Long duration turbo mode power limit
- Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
- Valid Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit1;
-
-/** Offset 0x084C - Package Short duration turbo mode power limit
- Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit2Power;
-
-/** Offset 0x0850 - Package PL3 power limit
- Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit3;
-
-/** Offset 0x0854 - Package PL4 power limit
- Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 PowerLimit4;
-
-/** Offset 0x0858 - Tcc Offset Time Window for RATL
- Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 TccOffsetTimeWindowForRatl;
-
-/** Offset 0x085C - Short term Power Limit value for custom cTDP level 1
- Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom1PowerLimit1;
-
-/** Offset 0x0860 - Long term Power Limit value for custom cTDP level 1
- Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom1PowerLimit2;
-
-/** Offset 0x0864 - Short term Power Limit value for custom cTDP level 2
- Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom2PowerLimit1;
-
-/** Offset 0x0868 - Long term Power Limit value for custom cTDP level 2
- Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom2PowerLimit2;
-
-/** Offset 0x086C - Short term Power Limit value for custom cTDP level 3
- Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom3PowerLimit1;
-
-/** Offset 0x0870 - Long term Power Limit value for custom cTDP level 3
- Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 4095875 in Step size of 125
-**/
- UINT32 Custom3PowerLimit2;
-
-/** Offset 0x0874 - Platform PL1 power
- Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
- 0 to 4095875 in Step size of 125
-**/
- UINT32 PsysPowerLimit1Power;
-
-/** Offset 0x0878 - Platform PL2 power
- Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
- 0 to 4095875 in Step size of 125
-**/
- UINT32 PsysPowerLimit2Power;
-
-/** Offset 0x087C - Platform Power Pmax
- PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
- Range 0-1024 Watts. Value of 800 = 100W
-**/
- UINT16 PsysPmax;
-
-/** Offset 0x087E - CpuS3ResumeDataSize
- Size of CPU S3 Resume Data
-**/
- UINT16 CpuS3ResumeDataSize;
-
-/** Offset 0x0880 - CpuS3ResumeData
- Pointer to CPU S3 Resume Data
-**/
- UINT32 CpuS3ResumeData;
-
-/** Offset 0x0884 - 5-Core Ratio Limit
- 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 FiveCoreRatioLimit;
-
-/** Offset 0x0885 - 6-Core Ratio Limit
- 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 SixCoreRatioLimit;
-
-/** Offset 0x0886 - 7-Core Ratio Limit
- 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 SevenCoreRatioLimit;
-
-/** Offset 0x0887 - 8-Core Ratio Limit
- 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
- 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
- to 1-Core Ratio Limit.Range is 0 to 83
-**/
- UINT8 EightCoreRatioLimit;
-
-/** Offset 0x0888 - Set Three Strike Counter Disable
- False (default): Three Strike counter will be incremented and True: Prevents Three
- Strike counter from incrementing; <b>0: False</b>; 1: True.
- 0: False, 1: True
-**/
- UINT8 ThreeStrikeCounterDisable;
-
-/** Offset 0x0889 - ReservedCpuPostMemTest
- Reserved for CPU Post-Mem Test
- $EN_DIS
-**/
- UINT8 ReservedCpuPostMemTest[1];
-
-/** Offset 0x088A - SgxSinitDataFromTpm
- SgxSinitDataFromTpm default values
-**/
- UINT8 SgxSinitDataFromTpm;
-
-/** Offset 0x088B - End of Post message
- Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
- EOP send in PEI, Send in DXE(0x2)(Default): EOP send in PEI
- 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
-**/
- UINT8 EndOfPostMessage;
-
-/** Offset 0x088C - D0I3 Setting for HECI Disable
- Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
- HECI devices
- $EN_DIS
-**/
- UINT8 DisableD0I3SettingForHeci;
-
-/** Offset 0x088D - Enable LOCKDOWN SMI
- Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
- $EN_DIS
-**/
- UINT8 PchLockDownGlobalSmi;
-
-/** Offset 0x088E - HD Audio Reset Wait Timer
- The delay timer after Azalia reset, the value is number of microseconds. Default is 600.
-**/
- UINT16 PchHdaResetWaitTimer;
-
-/** Offset 0x0890 - Enable LOCKDOWN BIOS Interface
- Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
- $EN_DIS
-**/
- UINT8 PchLockDownBiosInterface;
-
-/** Offset 0x0891 - RTC CMOS RAM LOCK
- Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
- and and lower 128-byte bank of RTC RAM.
- $EN_DIS
-**/
- UINT8 PchLockDownRtcLock;
-
-/** Offset 0x0892 - PCH Sbi lock bit
- This unlock the SBI lock bit to allow SBI after post time. 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchSbiUnlock;
-
-/** Offset 0x0893 - PCH Psf lock bit
- The PSF registers will be locked before 3rd party code execution. 0: Disable; 1: Enable.
- $EN_DIS
-**/
- UINT8 PchSbAccessUnlock;
-
-/** Offset 0x0894 - PCIE RP Ltr Max Snoop Latency
- Latency Tolerance Reporting, Max Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxSnoopLatency[24];
-
-/** Offset 0x08C4 - PCIE RP Ltr Max No Snoop Latency
- Latency Tolerance Reporting, Max Non-Snoop Latency.
-**/
- UINT16 PcieRpLtrMaxNoSnoopLatency[24];
-
-/** Offset 0x08F4 - PCIE RP Snoop Latency Override Mode
- Latency Tolerance Reporting, Snoop Latency Override Mode.
-**/
- UINT8 PcieRpSnoopLatencyOverrideMode[24];
-
-/** Offset 0x090C - PCIE RP Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Snoop Latency Override Multiplier.
-**/
- UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
-
-/** Offset 0x0924 - PCIE RP Snoop Latency Override Value
- Latency Tolerance Reporting, Snoop Latency Override Value.
-**/
- UINT16 PcieRpSnoopLatencyOverrideValue[24];
-
-/** Offset 0x0954 - PCIE RP Non Snoop Latency Override Mode
- Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
-**/
- UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
-
-/** Offset 0x096C - PCIE RP Non Snoop Latency Override Multiplier
- Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
-**/
- UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
-
-/** Offset 0x0984 - PCIE RP Non Snoop Latency Override Value
- Latency Tolerance Reporting, Non-Snoop Latency Override Value.
-**/
- UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
-
-/** Offset 0x09B4 - PCIE RP Slot Power Limit Scale
- Specifies scale used for slot power limit value. Leave as 0 to set to default.
-**/
- UINT8 PcieRpSlotPowerLimitScale[24];
-
-/** Offset 0x09CC - PCIE RP Slot Power Limit Value
- Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
-**/
- UINT16 PcieRpSlotPowerLimitValue[24];
-
-/** Offset 0x09FC - PCIE RP Upstream Port Transmiter Preset
- Used during Gen3 Link Equalization. Used for all lanes. Default is 5.
-**/
- UINT8 PcieRpUptp[24];
-
-/** Offset 0x0A14 - PCIE RP Downstream Port Transmiter Preset
- Used during Gen3 Link Equalization. Used for all lanes. Default is 7.
-**/
- UINT8 PcieRpDptp[24];
-
-/** Offset 0x0A2C - PCIE RP Enable Port8xh Decode
- This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
- 1: Enable.
- $EN_DIS
-**/
- UINT8 PcieEnablePort8xhDecode;
-
-/** Offset 0x0A2D - PCIE Port8xh Decode Port Index
- The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
-**/
- UINT8 PchPciePort8xhDecodePortIndex;
-
-/** Offset 0x0A2E - PCH Pm Disable Energy Report
- Disable/Enable PCH to CPU enery report feature.
- $EN_DIS
-**/
- UINT8 PchPmDisableEnergyReport;
-
-/** Offset 0x0A2F - PCH Pm Pmc Read Disable
- Deprecated
- $EN_DIS
-**/
- UINT8 PchPmPmcReadDisable;
-
-/** Offset 0x0A30 - PCH Sata Test Mode
- Allow entrance to the PCH SATA test modes.
- $EN_DIS
-**/
- UINT8 SataTestMode;
-
-/** Offset 0x0A31
-**/
- UINT8 ReservedFspsTestUpd[15];
-} FSP_S_TEST_CONFIG;
-
-/** Fsp S UPD Configuration
-**/
-typedef struct {
-
-/** Offset 0x0000
-**/
- FSP_UPD_HEADER FspUpdHeader;
-
-/** Offset 0x0020
-**/
- FSP_S_CONFIG FspsConfig;
-
-/** Offset 0x0780
-**/
- FSP_S_TEST_CONFIG FspsTestConfig;
-
-/** Offset 0x0A40
-**/
- UINT8 UnusedUpdSpace26[470];
-
-/** Offset 0x0C16
-**/
- UINT16 UpdTerminator;
-} FSPS_UPD;
-
-#pragma pack()
-
-#endif
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
deleted file mode 100644
index 248b4d5ef1..0000000000
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/** @file
-
-Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
-
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice, this
- list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice, this
- list of conditions and the following disclaimer in the documentation and/or
- other materials provided with the distribution.
-* Neither the name of Intel Corporation nor the names of its contributors may
- be used to endorse or promote products derived from this software without
- specific prior written permission.
-
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
- THE POSSIBILITY OF SUCH DAMAGE.
-
- This file is automatically generated. Please do NOT modify !!!
-
-**/
-#ifndef _MEM_INFO_HOB_H_
-#define _MEM_INFO_HOB_H_
-
-#pragma pack (push, 1)
-
-extern EFI_GUID gSiMemoryS3DataGuid;
-extern EFI_GUID gSiMemoryInfoDataGuid;
-extern EFI_GUID gSiMemoryPlatformDataGuid;
-
-#define MAX_NODE 1
-#define MAX_CH 2
-#define MAX_DIMM 2
-
-///
-/// Host reset states from MRC.
-///
-#define WARM_BOOT 2
-
-#define R_MC_CHNL_RANK_PRESENT 0x7C
-#define B_RANK0_PRS BIT0
-#define B_RANK1_PRS BIT1
-#define B_RANK2_PRS BIT4
-#define B_RANK3_PRS BIT5
-
-// @todo remove and use the MdePkg\Include\Pi\PiHob.h
-#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
-#ifndef __HOB__H__
-typedef struct _EFI_HOB_GENERIC_HEADER {
- UINT16 HobType;
- UINT16 HobLength;
- UINT32 Reserved;
-} EFI_HOB_GENERIC_HEADER;
-
-typedef struct _EFI_HOB_GUID_TYPE {
- EFI_HOB_GENERIC_HEADER Header;
- EFI_GUID Name;
- ///
- /// Guid specific data goes here
- ///
-} EFI_HOB_GUID_TYPE;
-#endif
-#endif
-
-///
-/// Defines taken from MRC so avoid having to include MrcInterface.h
-///
-
-//
-// Matches MAX_SPD_SAVE define in MRC
-//
-#ifndef MAX_SPD_SAVE
-#define MAX_SPD_SAVE 29
-#endif
-
-//
-// MRC version description.
-//
-typedef struct {
- UINT8 Major; ///< Major version number
- UINT8 Minor; ///< Minor version number
- UINT8 Rev; ///< Revision number
- UINT8 Build; ///< Build number
-} SiMrcVersion;
-
-//
-// Matches MrcDimmSts enum in MRC
-//
-#ifndef DIMM_ENABLED
-#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
-#endif
-#ifndef DIMM_DISABLED
-#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
-#endif
-#ifndef DIMM_PRESENT
-#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
-#endif
-#ifndef DIMM_NOT_PRESENT
-#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
-#endif
-
-//
-// Matches MrcBootMode enum in MRC
-//
-#ifndef bmCold
-#define bmCold 0 // Cold boot
-#endif
-#ifndef bmWarm
-#define bmWarm 1 // Warm boot
-#endif
-#ifndef bmS3
-#define bmS3 2 // S3 resume
-#endif
-#ifndef bmFast
-#define bmFast 3 // Fast boot
-#endif
-
-//
-// Matches MrcDdrType enum in MRC
-//
-#ifndef MRC_DDR_TYPE_DDR4
-#define MRC_DDR_TYPE_DDR4 0
-#endif
-#ifndef MRC_DDR_TYPE_DDR3
-#define MRC_DDR_TYPE_DDR3 1
-#endif
-#ifndef MRC_DDR_TYPE_LPDDR3
-#define MRC_DDR_TYPE_LPDDR3 2
-#endif
-#ifndef MRC_DDR_TYPE_UNKNOWN
-#define MRC_DDR_TYPE_UNKNOWN 3
-#endif
-
-#define MAX_PROFILE_NUM 4 // number of memory profiles supported
-#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
-
-//
-// DIMM timings
-//
-typedef struct {
- UINT32 tCK; ///< Memory cycle time, in femtoseconds.
- UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
- UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
- UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
- UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
- UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
- UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
- UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
- UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
- UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
- UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
- UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
- UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
- UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
- UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
- UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
- UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
- UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
-} MRC_CH_TIMING;
-
-typedef struct {
- UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
- UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
- UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
- UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
-} MRC_TA_TIMING;
-
-///
-/// Memory SMBIOS & OC Memory Data Hob
-///
-typedef struct {
- UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
- UINT8 DimmId;
- UINT32 DimmCapacity; ///< DIMM size in MBytes.
- UINT16 MfgId;
- UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
- UINT8 RankInDimm; ///< The number of ranks in this DIMM.
- UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
- UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
- UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
- UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
-} DIMM_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this channel should be used.
- UINT8 ChannelId;
- UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
- MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
- DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
-} CHANNEL_INFO;
-
-typedef struct {
- UINT8 Status; ///< Indicates whether this controller should be used.
- UINT16 DeviceId; ///< The PCI device id of this memory controller.
- UINT8 RevisionId; ///< The PCI revision id of this memory controller.
- UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
- CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
- MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
- MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
- MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
- MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
-} CONTROLLER_INFO;
-
-typedef struct {
- UINT8 Revision;
- UINT16 DataWidth; ///< Data width, in bits, of this memory device
- /** As defined in SMBIOS 3.0 spec
- Section 7.18.2 and Table 75
- **/
- UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
- UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
- UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
- /** As defined in SMBIOS 3.0 spec
- Section 7.17.3 and Table 72
- **/
- UINT8 ErrorCorrectionType;
-
- SiMrcVersion Version;
- BOOLEAN EccSupport;
- UINT8 MemoryProfile;
- UINT32 TotalPhysicalMemorySize;
- UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
- UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
- UINT8 Ratio;
- UINT8 RefClk;
- UINT32 VddVoltage[MAX_PROFILE_NUM];
- CONTROLLER_INFO Controller[MAX_NODE];
-} MEMORY_INFO_DATA_HOB;
-
-/**
- Memory Platform Data Hob
-
- <b>Revision 1:</b>
- - Initial version.
- <b>Revision 2:</b>
- - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
-**/
-typedef struct {
- UINT8 Revision;
- UINT8 Reserved[3];
- UINT32 BootMode;
- UINT32 TsegSize;
- UINT32 TsegBase;
- UINT32 PrmrrSize;
- UINT32 PrmrrBase;
- UINT32 GttBase;
- UINT32 MmioSize;
- UINT32 PciEBaseAddress;
-} MEMORY_PLATFORM_DATA;
-
-typedef struct {
- EFI_HOB_GUID_TYPE EfiHobGuidType;
- MEMORY_PLATFORM_DATA Data;
- UINT8 *Buffer;
-} MEMORY_PLATFORM_DATA_HOB;
-
-#pragma pack (pop)
-
-#endif // _MEM_INFO_HOB_H_
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 00:09:12 +0000