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| author | John Zhao <john.zhao@intel.com> | 2018-10-30 15:12:11 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-08 11:31:40 +0000 |
| commit | e673e5c09eebad3efbe19d15d064d131771abc2c (patch) | |
| tree | 2a2063231f69218f467e8d1ef53a3b091fe5b73a /src/vendorcode/intel/fsp | |
| parent | e05fa66b24fa8227cb8c4e7f5a9d98871a743f98 (diff) | |
| download | coreboot-e673e5c09eebad3efbe19d15d064d131771abc2c.tar.xz | |
soc/intel/apollolake: Improve cold boot and S3 resume
FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure
PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default
100ms to 10ms to improve cold boot and S3 resume performance.
BUG=b:118676361
CQ-DEPEND=CL:*703187
TEST=Verified system_resume_firmware_ec time reduction.
Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/vendorcode/intel/fsp')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index cc194b2240..18a43e2b8f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -1715,9 +1715,15 @@ typedef struct { **/ UINT8 SkipSpiPCP; -/** Offset 0x03AB +/** Offset 0x03AB - PMIC PCH_PWROK delay configuration - IPC Configuration + Upd for changing PCH_PWROK delay configuration : I2C_Slave_Address (31:24) + Register_Offset + (23:16) + OR Value (15:8) + AND Value (7:0) **/ - UINT8 ReservedFspsUpd[5]; + UINT32 PmicPmcIpcCtrl; + +/** Offset 0x03AF +**/ + UINT8 ReservedFspsUpd[1]; } FSP_S_CONFIG; /** Fsp S SGX Configuration |