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authorJohn Zhao <john.zhao@intel.com>2018-07-23 15:45:06 -0700
committerAaron Durbin <adurbin@chromium.org>2018-07-25 18:38:39 +0000
commite3816b4bc99fa8a5385943e1b47b4269a85b1877 (patch)
tree70615af3e70ce9ec88f16c9a72a95c099e10d927 /src/vendorcode/intel/fsp
parentdb70f3bb4d5d58441b1c93d216347ec296b4f787 (diff)
downloadcoreboot-e3816b4bc99fa8a5385943e1b47b4269a85b1877.tar.xz
vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.5
Update FSP header files to match FSP Reference Code Release v2.0.5 for Geminilake BUG=b:111683980 CQ-DEPEND=CL:*653835 Change-Id: Ib5ac532843fdb30ac3269fb6ed96dd05ef5736cc Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27623 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/fsp')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
index 1cbcb69991..cc194b2240 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
@@ -173,13 +173,13 @@ typedef struct {
Enable/Disable IPU Device. 0:Disable, 1:Enable(Default).
$EN_DIS
**/
- UINT8 IpuEn;
+ UINT8 IpuEnReserved;
/** Offset 0x003A - IMGU ACPI mode selection
0:Auto, 1:IGFX Child device(Default), 2:ACPI device.
0:Disable, 1:IGFX Child device, 2:ACPI device
**/
- UINT8 IpuAcpiMode;
+ UINT8 IpuAcpiModeReserved;
/** Offset 0x003B - Enable ForceWake
Enable/disable ForceWake Models. 0:Disable(Default), 1:Enable.
@@ -279,7 +279,7 @@ typedef struct {
Enable/disable SaIpuEnable. 0:Disable(Default), 1:Enable.
$EN_DIS
**/
- UINT8 SaIpuEnable;
+ UINT8 SaIpuEnableReserved;
/** Offset 0x0052 - GT PM Support
Enable/Disable GT power management support. 0:Disable, 1:Enable(Default).