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authorKane Chen <kane.chen@intel.com>2018-08-03 09:39:57 +0800
committerPatrick Georgi <pgeorgi@google.com>2018-08-06 07:56:47 +0000
commitc024381f8f1916607a8e5ee209063d17d37a5a61 (patch)
treef6e92ccc832c04698bc0a0b1d8d62e4efdafeebf /src/vendorcode/intel
parenta8b4b75d241b0ae03cc2f11589339515afa41773 (diff)
downloadcoreboot-c024381f8f1916607a8e5ee209063d17d37a5a61.tar.xz
vendorcode/intel/fsp/fsp2_0/glk: Add nWR config in Odt Config
From doc 571118, the bit 5 of OdtConfig is nWR config. If the bit 5 is set, MRC will set MR1 nWR field to 24. If the bit 5 is clear, MRC will set MR1 nWR field to 6. Change-Id: Ic8e4e2ffb098c8ba2f670535981e9a30c3d45b64 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/27814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/intel')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
index c25fd406e5..0329c939c0 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
@@ -474,6 +474,7 @@ typedef struct {
1 - ODT_AB_HIGH_HIGH. DDR3L & LPDDR3: X - Don't Care. [4] TX ODT. DDR3L only:
0 = RZQ/4 (60 Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_60_OHMS, 1 = RZQ/2 (120
Ohms) = MRC_SMIP_DDR3L_TX_ODT_RTT_WR_120_OHMS. LPDDR3 & LPDDR4: X = Don't Care
+ [5] nWR config: 0 - nWR6, 1 - nWR24.
**/
UINT8 Ch0_OdtConfig;