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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-17 06:47:50 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-21 07:01:23 +0000 |
| commit | 8e23bac97ec66a49f9ddb1a4069e4e68666833fb (patch) | |
| tree | 92d982a32199bc827e59dc7d8da48a96e5d98599 /src/vendorcode/intel | |
| parent | 12b121cdb450d96309dd96b2ccc25fc5501d2250 (diff) | |
| download | coreboot-8e23bac97ec66a49f9ddb1a4069e4e68666833fb.tar.xz | |
intel/fsp1_0,baytrail,rangeley: Tidy up use of preprocessor
Remove cases of __PRE_RAM__ and other preprocessor guards.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34928
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c index ba56543975..bbcf753dce 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c @@ -43,9 +43,7 @@ are permitted provided that the following conditions are met: // // Pointer to the HOB should be initialized with the output of FSP INIT PARAMS // -#ifndef __PRE_RAM__ extern volatile void *FspHobListPtr; -#endif /** Reads a 64-bit value from memory that may be unaligned. @@ -116,12 +114,8 @@ GetHobList ( VOID ) { -#ifndef __PRE_RAM__ ASSERT (FspHobListPtr != NULL); return ((VOID *)FspHobListPtr); -#else - return ((VOID *)NULL); -#endif } /** |