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| author | zbao <fishbaozi@gmail.com> | 2016-05-24 21:21:26 +0800 |
|---|---|---|
| committer | Zheng Bao <fishbaozi@gmail.com> | 2016-05-30 06:09:21 +0200 |
| commit | e0849350aa74c58751675da389d717a93c365030 (patch) | |
| tree | 554128e545f0fa425d27e7bd2830c469954af7f2 /src/vendorcode/intel | |
| parent | 69088c2825d9bcee7b2cfae699b648ed33e0c7d7 (diff) | |
| download | coreboot-e0849350aa74c58751675da389d717a93c365030.tar.xz | |
AMD/spi: Do not reset fifo after skipping the sent bytes
After we skip the bytes we send, the fifo pointer is at
right position. Reseting the fifo will change it to a
wrong place.
Please view the flashrom code, which tells the same thing.
https://code.coreboot.org/p/flashrom/source/tree/HEAD/trunk/sb600spi.c#L257
Change-Id: I31d487ce32c0d7ca3dead36d2b14611e73b1ad60
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/14955
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/intel')
0 files changed, 0 insertions, 0 deletions