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| author | Martin Roth <gaumless@gmail.com> | 2014-04-04 11:59:48 -0600 |
|---|---|---|
| committer | Martin Roth <martin.roth@se-eng.com> | 2014-04-11 17:24:39 +0200 |
| commit | 18a40e05334b650d8104787416afd8ba87f03987 (patch) | |
| tree | ba90ff837327f8c2c8c09806b061fab6d5435c43 /src/vendorcode/intel | |
| parent | eb4920df327fd7d3ac9e9f853768b15e9a02a9b1 (diff) | |
| download | coreboot-18a40e05334b650d8104787416afd8ba87f03987.tar.xz | |
Update vendorcode/intel/makefile for coming FSPs
Other FSPs have more than just the initial fsphob.c source file.
Add any .c files in the srx directory to the ramstage build.
Change-Id: I5118bdcca44935b579809c4fc9566ab7914a6e4b
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/Makefile.inc | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/vendorcode/intel/Makefile.inc b/src/vendorcode/intel/Makefile.inc index b05838f52a..8569af03ce 100644 --- a/src/vendorcode/intel/Makefile.inc +++ b/src/vendorcode/intel/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2013 Sage Electronic Engineering, LLC. +## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,8 +17,11 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ifneq ($(CONFIG_FSP_VENDORCODE_HEADER_PATH),) +ifneq ($(CONFIG_FSP_VENDORCODE_HEADER_PATH),) FSP_PATH := $(call strip_quotes,$(CONFIG_FSP_VENDORCODE_HEADER_PATH)) -ramstage-y += $(FSP_PATH)srx/fsphob.c +FSP_SRC_FILES := $(wildcard src/vendorcode/intel/$(FSP_PATH)srx/*.c) +FSP_C_INPUTS := $(foreach file, $(FSP_SRC_FILES), $(FSP_PATH)srx/$(notdir $(file))) +ramstage-y += $(FSP_C_INPUTS) + CC := $(CC) -Isrc/vendorcode/intel/$(FSP_PATH)include -endif
\ No newline at end of file +endif |