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| author | Peter Lemenkov <lemenkov@gmail.com> | 2018-10-19 16:57:27 +0200 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2018-10-23 06:15:43 +0000 |
| commit | 5797b2eb05ec46d877a2ae6b5e0c517ae54a6fe8 (patch) | |
| tree | 1b23efeb6e987f4886ffd5afa12418234eb988b4 /src/vendorcode/intel | |
| parent | 39315985e89e6ef3e7c01e697faf439280045157 (diff) | |
| download | coreboot-5797b2eb05ec46d877a2ae6b5e0c517ae54a6fe8.tar.xz | |
src: Typo fix (cosmetic)
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29196
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h index 12c6e4413c..d03a844037 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h @@ -2978,8 +2978,8 @@ typedef struct { **/ UINT8 ThreeStrikeCounterDisable; -/** Offset 0x0899 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable. +/** Offset 0x0899 - Set HW P-State Interrupts Enabled for MISC_PWR_MGMT + Set HW P-State Interrupts Enabled for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable. $EN_DIS **/ UINT8 HwpInterruptControl; |