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authorLee Leahy <leroy.p.leahy@intel.com>2016-08-06 09:51:35 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-08-10 22:31:52 +0200
commit5e07a7e474eb2ceeb252ddc33fb26fe041425c1b (patch)
treec8d65f11a3197dece346ef23528ac6ac6b434aee /src/vendorcode/intel
parent00a38a4a9e668caf573517051aafff9eba61def3 (diff)
downloadcoreboot-5e07a7e474eb2ceeb252ddc33fb26fe041425c1b.tar.xz
soc/intel/quark: Switch to using serial routines for FSP
Switch from passing FSP the serial port address to passing FSP the serial port output routine. This enables coreboot to use any UART in the system and also log the FSP output. TEST=Build and run on Galileo Gen2 Change-Id: I67d820ea0360a3188480455dd2595be7f2debd5c Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/16105 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/intel')
-rw-r--r--src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h21
1 files changed, 15 insertions, 6 deletions
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
index c27a156624..743e4ee861 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -88,7 +88,7 @@ typedef struct {
UINT32 RmuLength;
/** Offset 0x0030
**/
- UINT32 SerialPortBaseAddress;
+ UINT32 Reserved_30;
/** Offset 0x0034
**/
UINT32 tRAS;
@@ -175,17 +175,26 @@ typedef struct {
UINT32 MrcDataLength;
/** Offset 0x0068
**/
- UINT8 ReservedMemoryInitUpd[8];
+ UINT32 SerialPortPollForChar;
+/** Offset 0x006C
+**/
+ UINT32 SerialPortReadChar;
+/** Offset 0x0070
+**/
+ UINT32 SerialPortWriteChar;
+/** Offset 0x0074
+**/
+ UINT8 ReservedMemoryInitUpd[12];
} MEMORY_INIT_UPD;
typedef struct {
-/** Offset 0x0070
+/** Offset 0x0080
**/
UINT64 Signature;
-/** Offset 0x0078
+/** Offset 0x0088
**/
UINT64 Revision;
-/** Offset 0x0080
+/** Offset 0x0090
**/
UINT16 PcdRegionTerminator;
} SILICON_INIT_UPD;
@@ -210,7 +219,7 @@ typedef struct _UPD_DATA_REGION {
/** Offset 0x0018
**/
MEMORY_INIT_UPD MemoryInitUpd;
-/** Offset 0x0070
+/** Offset 0x0080
**/
SILICON_INIT_UPD SiliconInitUpd;
} UPD_DATA_REGION;