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| author | Xi Chen <xixi.chen@mediatek.com> | 2021-03-12 11:15:45 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-03-16 03:50:05 +0000 |
| commit | b8f03fd0cadffdd735cc0951b73e9460a58c9b1f (patch) | |
| tree | 276393480c832b0e56aefa69e527f5a51c1168b2 /src/vendorcode/mediatek | |
| parent | 995eed9fef467fd8c7cf76b0502dfa8da037028e (diff) | |
| download | coreboot-b8f03fd0cadffdd735cc0951b73e9460a58c9b1f.tar.xz | |
vendorcode/mt8192: fix fast-k gating PI P1 initialization
In RX Gating flow, PI P1 delay is missing, so re-add the initialization.
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: Ic72ccecd205062ee79f6928993fac772fc10f880
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/vendorcode/mediatek')
| -rw-r--r-- | src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c index 1181cdca8c..1540770072 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_calibration_api.c @@ -4586,6 +4586,7 @@ static void rxdqs_gating_fastk_save_restore(DRAMC_CTX_T *p, best_win->best_dqsien_dly_ui_p1[dqs_i] / ui_per_mck; best_win->best_dqsien_dly_ui_p1[dqs_i] = best_win->best_dqsien_dly_ui_p1[dqs_i] % ui_per_mck; + best_win->best_dqsien_dly_pi_p1[dqs_i] = best_win->best_dqsien_dly_pi[dqs_i]; vSetCalibrationResult(p, DRAM_CALIBRATION_GATING, DRAM_FAST_K); |