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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-07-19 16:19:46 +0530
committerAaron Durbin <adurbin@chromium.org>2017-07-25 14:58:10 +0000
commit50987a7b9e08139829da84958deea7f8bde3d376 (patch)
tree14068aa35efd6b7732b3669cb5c5016fe2fb2836 /src/vendorcode
parent8e51319b03894d7a838db247a4969ccef8969c13 (diff)
downloadcoreboot-50987a7b9e08139829da84958deea7f8bde3d376.tar.xz
vendercode/intel/fsp/skykabylake: Add new UPD SpiFlashCfgLockDown
A new UPD named SpiFlashCfgLockDown is added in the FSP-S header file. This change is going to come in FSP in the next FSP release. This patch is pushed to urgently fix the SPI FPR locking issue. CQ-DEPEND=CL:*414049 BUG=b:63049493 BRANCH=none TEST=Built and boot poppy Change-Id: I4725506103781a358b18ee70f4fdd56bf4ab3d96 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h11
1 files changed, 9 insertions, 2 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
index e91bc796bf..b3c7698857 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h
@@ -165,9 +165,16 @@ typedef struct {
**/
UINT8 ShowSpiController;
-/** Offset 0x0036
+/** Offset 0x0036 - Flash Configuration Lock Down
+ Enable/disable flash lock down. If platform decides to skip this programming, it
+ must lock SPI flash register before end of post.
+ $EN_DIS
+**/
+ UINT8 SpiFlashCfgLockDown;
+
+/** Offset 0x0037
**/
- UINT8 UnusedUpdSpace0[2];
+ UINT8 UnusedUpdSpace0;
/** Offset 0x0038 - MicrocodeRegionBase
Memory Base of Microcode Updates