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authorBarnali Sarkar <barnali.sarkar@intel.com>2017-07-19 16:09:56 +0530
committerAaron Durbin <adurbin@chromium.org>2017-07-25 14:56:13 +0000
commit8e51319b03894d7a838db247a4969ccef8969c13 (patch)
treed690c03b8b8c688f3981cf3bd78fcf0845ecb7ab /src/vendorcode
parent4635787895a5f30b573e1e34ddbf723588ff847a (diff)
downloadcoreboot-8e51319b03894d7a838db247a4969ccef8969c13.tar.xz
soc/intel/common/block: Modify fast_spi_lock_bar function
Use 16bit write to avoid touching the upper two bytes that may cause write cycle to fail in case a prior transaction has not completed. This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN, writing both in the same cycle is guaranteed to work by design. Avoid read->modify->write operation not to clear the RW1C bits unintentionally. Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/20643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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