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| author | Patrick Georgi <pgeorgi@google.com> | 2021-05-12 16:39:09 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-13 18:52:46 +0000 |
| commit | c8d3b9160a3c33a1bcdd2c417db6fc402ac82c02 (patch) | |
| tree | b5d00724291f42d1a42e04ab49fa95cf6ccfb2f7 /src/vendorcode | |
| parent | 99973d29af774c54e8859d967b2b9617abebeeb0 (diff) | |
| download | coreboot-c8d3b9160a3c33a1bcdd2c417db6fc402ac82c02.tar.xz | |
vc/mediatek: Align code indent with code flow
gcc 11 suspects missing braces here, but it seems the line should be
executed in all cases, so unindent it.
Change-Id: I7b8cacd48e86284c5145c4e8ffb6add75a743108
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c index cd897ed917..ffdf3d6850 100644 --- a/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c +++ b/src/vendorcode/mediatek/mt8192/dramc/dramc_pi_basic_api.c @@ -3097,8 +3097,8 @@ void TXPICGSetting(DRAMC_CTX_T * p) else u2COMB_TX_SEL[1] = (u4DQ_OEN_final > u2Shift_DQ_Div[1])? ((u4DQ_OEN_final - u2Shift_DQ_Div[1]) >> u1Div_ratio): 0; - vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) - | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); + vIO32WriteFldMulti(DRAMC_REG_ADDR(DRAMC_REG_SHURK_APHY_TX_PICG_CTRL), P_Fld(u2COMB_TX_SEL[0], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P0) + | P_Fld(u2COMB_TX_SEL[1], SHURK_APHY_TX_PICG_CTRL_DDRPHY_CLK_EN_COMB_TX_DQ_RK_SEL_P1)); } vSetRank(p, u1Rank_bak); } |