diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-08-26 14:58:29 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-10 09:43:13 +0000 |
| commit | a887492e1e51849b75c7bb0d67430be4b1074493 (patch) | |
| tree | 37d52033d2b8f0cde47851cf0a8e71c38dec88c6 /src/vendorcode | |
| parent | a7c609c262d5beba968519903fed297dc4b601c1 (diff) | |
| download | coreboot-a887492e1e51849b75c7bb0d67430be4b1074493.tar.xz | |
FSP: Pass FSP image base address to find_fsp
Add a parameter to find_fsp which is the image base address. Adjust the
fake stack in cache_as_ram.inc to pass in the read-only FSP image base
address. In fsp_notify, pass in the read-only FSP image base address
when the FSP header pointer is NULL. In find_fsp, validate the FSP
binary image starting from the specified image base address.
BRANCH=none
BUG=None
TEST=Build and run on Skylake
Change-Id: Iac43c8aac8491390479af551765b514ca919928a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 592dae53f3b32694190cc5cb0fa6ca94df68aa95
Original-Change-Id: I7d6a415458a81f3b6bcdcfc9a90eceb2ac22144e
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295593
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11545
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode')
0 files changed, 0 insertions, 0 deletions