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author | Paul Kocialkowski <contact@paulk.fr> | 2015-09-22 22:16:33 +0200 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2015-10-17 18:10:29 +0000 |
commit | 3414561f00f49266580fa9372a24ef8578c7d932 (patch) | |
tree | a46bfc3474c2922caf9517d46b6e3353a2ffb7cb /src/vendorcode | |
parent | 285111f822f38124df488514e34298ce1a1e341c (diff) | |
download | coreboot-3414561f00f49266580fa9372a24ef8578c7d932.tar.xz |
armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write
Some registers only allow word-sized or half-word-sized operations and will
cause a data fault when accessed with byte-sized operations.
However, the compiler may or may not break such an operation into smaller
(byte-sized) chunks. Thus, we need to reliably perform word-sized operations for
32 bit read/write and half-word-sized operations for 16 bit read/write.
This is particularly the case on the rk3288 SRAM registers, where the watchdog
tombstone is stored. Moving to GCC 5.2.0 introduced a change of strategy in the
compiler, where a 32 bit read would be broken into byte-sized chunks, which
caused a data fault when accessing the watchdog tombstone register.
The definitions for byte-sized memory operations are also adapted to stay
consistent with the rest.
Change-Id: I1fb3fc139e0a813acf9d70f14386a9603c9f9ede
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11698
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Diffstat (limited to 'src/vendorcode')
0 files changed, 0 insertions, 0 deletions