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authorJacob Garber <jgarber1@ualberta.ca>2019-04-03 15:46:24 -0600
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-04-07 03:27:52 +0000
commit4318a978a7a7ded371cdb3faf88b70fb99cbdb41 (patch)
treec162afe32f732930e0959b6dd84e6d256845638b /src/vendorcode
parent7eb8eed460ccc8d2b9d7ad87bf165c12e894eaba (diff)
downloadcoreboot-4318a978a7a7ded371cdb3faf88b70fb99cbdb41.tar.xz
vc/amd/agesa/f14: Add missing break statement
We do not want to ASSERT(FALSE). Found-by: Coverity Scan, CID 1241850 (MISSING_BREAK) Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Change-Id: Ia08bb519cdb5ef5d2a79898706c7fac7e58adf3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/32180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
index 7fb195d4bc..daf529c367 100644
--- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnS3.c
@@ -792,6 +792,7 @@ MemNS3GetSetBitField (
break;
case AccessS3SaveWidth32:
RegValue = *(UINT32 *) Value;
+ break;
default:
ASSERT (FALSE);
}