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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2018-04-20 16:34:40 -0700
committerAaron Durbin <adurbin@chromium.org>2018-04-27 03:25:43 +0000
commit6cc813a5e9b557d10af8bb26f2a9d48ab4c9510d (patch)
tree3e65283c7705ebc47b7b46394305cf5690e0683c /src/vendorcode
parent94984a846166c7ac927fcfcb2b34c1bfeabf8fcf (diff)
downloadcoreboot-6cc813a5e9b557d10af8bb26f2a9d48ab4c9510d.tar.xz
vendorcode/intel: Update GLK FSP Header files w.r.t FSP v2.0.2
Update FSP header files to match FSP Reference Code Release v2.0.2 for Gemimilake CQ-DEPEND=CL:*594651,CL:*598345 Change-Id: I78d064db41a54d97e98d6e44e0832724127e5bfc Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h11
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h71
2 files changed, 76 insertions, 6 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
index 4559e225d2..1898c09976 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h
@@ -993,7 +993,12 @@ typedef struct {
**/
UINT32 RootPort5Perst;
-/** Offset 0x017C
+/** Offset 0x017C - CpuPeiApWakeupBufferAddr
+ Address for CpuPeiApWakeupBuffer.
+**/
+ UINT32 CpuPeiApWakeupBufferAddr;
+
+/** Offset 0x0180
**/
UINT8 ReservedFspmUpd[4];
} FSP_M_CONFIG;
@@ -1014,9 +1019,9 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0180
+/** Offset 0x0184
**/
- UINT8 UnusedUpdSpace1[134];
+ UINT8 UnusedUpdSpace1[130];
/** Offset 0x0206
**/
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
index cc50058d57..970f0e2d89 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h
@@ -1701,11 +1701,72 @@ typedef struct {
**/
UINT8 ProcessorTraceOutputScheme;
-/** Offset 0x03A9
+/** Offset 0x03A9 - USB PDO Programming
+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+ during later phase. 1: enable, 0: disable
+ 1: enable, 0: disable
**/
- UINT8 ReservedFspsUpd[7];
+ UINT8 UsbPdoProgramming;
+
+/** Offset 0x03AA
+**/
+ UINT8 ReservedFspsUpd[6];
} FSP_S_CONFIG;
+/** Fsp S SGX Configuration
+**/
+typedef struct {
+
+/** Offset 0x03C0
+**/
+ UINT32 Signature;
+
+/** Offset 0x03C4 - Selective enable SGX
+ Selective enable SGX. 0xFFFF(Default).
+**/
+ UINT16 SelectiveEnableSgx;
+
+/** Offset 0x03C6 - SGX debug mode
+ Select SGX mode. 0:Disable(default), 1:Enable
+ 0:Disable(default), 1:Enable
+**/
+ UINT8 SgxDebugMode;
+
+/** Offset 0x03C7 - SGX Launch Control Policy Mode
+ Select Launch Control Policy Mode. 0:Intel - Default, 1:Per-boot Select mode(default)
+ 0:Intel locked , 1:Unlocked mode(default) , 2: Locked mode
+**/
+ UINT8 SgxLcp;
+
+/** Offset 0x03C8 - LE KeyHash0
+ LE KeyHash0. 0x0(Default).
+**/
+ UINT64 SgxLePubKeyHash0;
+
+/** Offset 0x03D0 - LE KeyHash1
+ LE KeyHash1. 0x0(Default).
+**/
+ UINT64 SgxLePubKeyHash1;
+
+/** Offset 0x03D8 - LE KeyHash2
+ LE KeyHash2. 0x0(Default).
+**/
+ UINT64 SgxLePubKeyHash2;
+
+/** Offset 0x03E0
+**/
+ UINT8 UnusedUpdSpace8[16];
+
+/** Offset 0x03F0 - LE KeyHash3
+ LE KeyHash3. 0x0(Default).
+**/
+ UINT64 SgxLePubKeyHash3;
+
+/** Offset 0x03F8
+**/
+ UINT8 ReservedFspsSgxUpd[6];
+} FSP_S_SGX_CONFIG;
+
/** Fsp S UPD Configuration
**/
typedef struct {
@@ -1720,7 +1781,11 @@ typedef struct {
/** Offset 0x03B0
**/
- UINT8 UnusedUpdSpace7[78];
+ UINT8 UnusedUpdSpace7[16];
+
+/** Offset 0x03C0
+**/
+ FSP_S_SGX_CONFIG FspsSgxConfig;
/** Offset 0x03FE
**/